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Ryan Chen <[email protected]> says:
AST2700 is the 8th generation of Integrated Remote Management
Processor introduced by ASPEED Technology Inc. It is a Board
Management Controller (BMC) SoC family with a dual-die architecture:
SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs,
clock dividers and reset domains.
Link: https://lore.kernel.org/r/[email protected]
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Add a SDRAM controller driver for the AST2700, derived from the
existing AST2700 controller code used by the Ibex SPL but adapted
to run from ARM U-Boot proper on the Cortex-A35 cores.
The DDR4/DDR5 controller and its DesignWare PHY are programmed by
the Ibex SPL before ARM U-Boot proper takes over. This driver
reads back the configuration left by the SPL, probes the
controller, and exposes ram_info (base and size, with the VGA
carve-out subtracted) via UCLASS_RAM so that dram_init() can
populate gd->ram_size.
The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*)
are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub
when ARM U-Boot proper is the caller; the real implementation is
provided by the Ibex SPL via the same fmc_hdr.h descriptor format
(here added for the ARM build).
Adds the supporting register-layout headers under
arch/arm/include/asm/arch-aspeed/:
- sdram.h: SDRAM controller and DWC PHY register definitions
- scu.h: SCU bits referenced by the SDRAM driver
- fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with
arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used
by the Ibex SPL)
Signed-off-by: Ryan Chen <[email protected]>
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Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35)
Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th
generation BMC and uses a dual-die architecture: SoC0 (the "CPU"
die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000,
while SoC1 (the "IO" die) hosts the peripherals and its own SCU at
0x14c02000.
This commit adds:
- ASPEED_AST2700 Kconfig option and the ast2700 mach subdir
(mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*)
- arm64 MMU map covering the SoC device window and the DRAM
region at 0x4_0000_0000 (up to 8 GiB)
- lowlevel_init.S for early CPU bring-up
- cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants)
and reset cause (cold reset, EXT reset, WDT reset)
- board_common: dram_init via UCLASS_RAM, AHBC timeout init
- platform: env_get_location() that selects SPI/eMMC based on
the IO-die HW strap; arch_misc_init() that exposes
${boot_device} and ${verify} to the boot script
- SCU0/SCU1 register layout header (scu_ast2700.h)
- configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h
for the AST2700 EVB board
The defconfig depends on ast2700-evb.dts, which is introduced in
a subsequent patch; this commit must be applied with the
remaining series for evb-ast2700_defconfig to build.
Signed-off-by: Ryan Chen <[email protected]>
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Add V2X Get State API to return V2X states for debug purpose
Signed-off-by: Ye Li <[email protected]>
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The LDB clock sources don't have to be the same, so allow DI1 clock to
be configured separately.
Unlikely to be significant, but the reason will become apparent in the
following commit.
Signed-off-by: Brian Ruley <[email protected]>
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Prepare v2026.07-rc5
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set_one_region()"
Casey Connolly <[email protected]> says:
Currently trying to unmap a region results in slow and largely broken
behaviour as we unnecessarily split blocks and manually set thousands of
individual 4k pages instead of higher level blocks.
This series fixes the behaviour of set_one_region() so that it works
properly when called to unmap regions. See patch 4 for details.
Patches 1 & 2 improve the existing debug functionality, the pagetable
dumper will now print most explicitly unmapped regions (since they still
have their PA intact), as well as adding a new function which does a
very basic software TLB lookup to help with debugging.
Patch 3 de-duplicates some code by moving the loop that always surrounds
set_one_region() calls into its own function, this also helps with
readability in the calling functions.
Link: https://lore.kernel.org/r/[email protected]
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Implement a super basic software TLB walk which can look up a single
address in the TLB and print each stage of the translation. This is
helpful for debugging TLB issues and will be compiled out if unused.
Example output on QEMU aarch64:
Performing software TLB lookup of address 0x50100000 va_bits: 40
PTE: 0x47fe0000. addr[47:39]: 0x000 (offset 0x00000)
L0: 0x47fe0000 -> TABLE (0x47fe1000)
PTE: 0x47fe1000. addr[38:30]: 0x001 (offset 0x00008)
L1: 0x47fe1008 -> BLOCK (0x40000000)
[0x40000000 - 0x80000000]
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Casey Connolly <[email protected]>
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Bastien Curutchet <[email protected]> says:
This series aims to add back the omap4 support. This support was removed
by commit b0ee3fe642c ("arm: ti: Remove omap4 platform support") because
at that moment, none of the OMAP4-based boards had done the migration to
DM_I2C.
My use case is an old product based on the Variscite's omap4 system on
module. I needed to upgrade U-Boot on it for security reasons. I think
that this work could benefit to other people who may have same kind of
product to maintain.
Patch 1 to 3 remove the omap's clock driver dependency to the AM33xx
as it is also present in omap4 platforms. I tested these changes on the
beaglebone black to ensure I didn't break the AM33xx case.
Patch 4 & 5 revert the deletion of the omap4 support. The revert makes
checkpatch.pl angry. I fixed quite a lots of warnings already but it
remains two kinds of warnings:
- CamelCase on timings structure, I left the CamelCase because IMHO it's
more readable this way.
- #ifdef CONFIG_XYZ shouldn't be used anymore. I left one of this because
I didn't find a clean way to get rid of it.
Patch 6 adds support for the Variscite's system on module. This system on
module is supported by the Linux project through
ti/omap/omap4-var-som-om44.dtsi
Link: https://lore.kernel.org/r/[email protected]
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OMAP4 support is present but there isn't any board using it.
Add minimal support for the Variscite OMAP4-SoM (debug console + boot
from SD card).
Use the ti/omap/omap4-var-stk-om44 device-tree from the Linux kernel. The
real representation of the SoM's hardware is located in
ti/omap/omap4-var-som-om44.dtsi included in it.
Set myself as maintainer for it.
Signed-off-by: Bastien Curutchet <[email protected]>
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omap4 support was dropped by b0ee3fe642c ("arm: ti: Remove omap4 platform
support") because the supported boards hadn't done the conversion to
CONFIG_DM_I2C in time. It still exists some omap4-based products and
they could benefit from the latest U-Boot support for obvious security
reasons.
Revert part of b0ee3fe642c to introduce back a minimal support for the
omap4 platform.
Fix the checkpatch's warning/errors induced by this revert. Following
warnings are still present:
| arch/arm/include/asm/arch-omap4/clock.h:445: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
| arch/arm/mach-omap2/omap4/hwinit.c:24: WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where possible
| arch/arm/mach-omap2/omap4/sdram_elpida.c:142: CHECK: Avoid CamelCase: <tRPab>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:143: CHECK: Avoid CamelCase: <tRCD>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:144: CHECK: Avoid CamelCase: <tWR>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:145: CHECK: Avoid CamelCase: <tRASmin>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:146: CHECK: Avoid CamelCase: <tRRD>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:147: CHECK: Avoid CamelCase: <tWTRx2>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:148: CHECK: Avoid CamelCase: <tXSR>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:149: CHECK: Avoid CamelCase: <tXPx2>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:150: CHECK: Avoid CamelCase: <tRFCab>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:151: CHECK: Avoid CamelCase: <tRTPx2>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:152: CHECK: Avoid CamelCase: <tCKE>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:153: CHECK: Avoid CamelCase: <tCKESR>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:154: CHECK: Avoid CamelCase: <tZQCS>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:155: CHECK: Avoid CamelCase: <tZQCL>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:156: CHECK: Avoid CamelCase: <tZQINIT>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:157: CHECK: Avoid CamelCase: <tDQSCKMAXx2>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:158: CHECK: Avoid CamelCase: <tRASmax>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:159: CHECK: Avoid CamelCase: <tFAW>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:209: CHECK: Avoid CamelCase: <tRL>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:210: CHECK: Avoid CamelCase: <tRP_AB>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:213: CHECK: Avoid CamelCase: <tRAS_MIN>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:215: CHECK: Avoid CamelCase: <tWTR>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:216: CHECK: Avoid CamelCase: <tXP>
| arch/arm/mach-omap2/omap4/sdram_elpida.c:217: CHECK: Avoid CamelCase: <tRTP>
I didn't find an clean way to fix the "don't use #ifdef" warning as we
need to define the gpio_bank for the SPL build only.
For the CamelCase warnings, the incriminated attributes represent
timings, so IMHO, it is more readable with CamelCase.
Set myself as OMAP4 maintainer.
Signed-off-by: Bastien Curutchet <[email protected]>
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Lots of clock definitions are common to OMAP3, OMAP4 and OMAP5. So the
same macros are defined both in arch-am33xx/clock.h and in
arch-omap5/clock.h. Upcoming support for OMAP4 will again need the same
macros.
Group these common macro definitions into a common omap_clock header
shared across the OMAP2+ families.
Signed-off-by: Bastien Curutchet <[email protected]>
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PRM_VC_I2C_CHANNEL_FREQ_KHZ is defined in omap5/clock.h but isn't really
related to clocks.
Since it's only used by mach-omap2/vc.c, move its definition there.
Signed-off-by: Bastien Curutchet <[email protected]>
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Rockchip RK3576 SoC has two built-in GMACs which connect to external PHYs
via RGMII interface. The RGMII link can be clocked by either the PHY or
the SoC. When the SoC is the master, as is the case on the RK3576 EVB1,
the output clock needs to be configured in the CRU.
Add the respective logic for getting and setting the RGMII reference clock
output for both GMAC0 and GMAC1.
Signed-off-by: Alexey Charkov <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Disable relevant modules in kernel FDT and u-boot FDT according to
fuse settings on iMX95/94/952.
For u-boot FDT fixup, introduce a common function that each board
needs this fixup could select OF_BOARD_FIXUP and implement
board_fix_fdt to call imx9_uboot_fixup_by_fuse.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add support for the on-die Thermal Monitoring Unit (TMU) of the
new QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...):
examples on a lx2160:
=> temperature list
| Device | Driver | Parent
| tmu@1f80000 | imx_tmu | root_driver
| cluster67-thermal | imx_tmu | tmu@1f80000
| ddr1-cluster5-thermal | imx_tmu | tmu@1f80000
| wriop-thermal | imx_tmu | tmu@1f80000
| dce-qbman-hsio2-thermal | imx_tmu | tmu@1f80000
| ccn-dpaa-tbu-thermal | imx_tmu | tmu@1f80000
| cluster4-hsio3-thermal | imx_tmu | tmu@1f80000
| cluster23-thermal | imx_tmu | tmu@1f80000
=> temperature get tmu@1f80000
tmu@1f80000: 82000 mC
=> temperature get wriop-thermal
wriop-thermal: 81000 mC
The parent tmu@... node owns the MMIO and calibration; one
UCLASS_THERMAL device is bound per/thermal-zones site so each shows
up by its zone name:
=> dm tree
...
thermal 2 [ + ] imx_tmu |-- tmu@1f80000
thermal 3 [ + ] imx_tmu | |-- cluster67-thermal
thermal 4 [ + ] imx_tmu | |-- ddr1-cluster5-thermal
thermal 5 [ + ] imx_tmu | |-- wriop-thermal
thermal 6 [ + ] imx_tmu | |-- dce-qbman-hsio2-thermal
thermal 7 [ + ] imx_tmu | |-- ccn-dpaa-tbu-thermal
thermal 8 [ + ] imx_tmu | |-- cluster4-hsio3-thermal
thermal 9 [ + ] imx_tmu | `-- cluster23-thermal
...
The dtsi additions mirror the existing fsl-ls1028a.dtsi: the LX2160A
SoC dtsi gains the tmu@1f80000 node plus a thermal-zones hierarchy
with 7 sites:
cluster67-thermal site 0 A72 clusters 6 + 7
ddr1-cluster5-thermal site 1 DDR1 + A72 cluster 5
wriop-thermal site 2 WRIOP
dce-qbman-hsio2-thermal site 3 DCE + QBMAN + HSIO2
ccn-dpaa-tbu-thermal site 4 CCN508 + DPAA + TBU
cluster4-hsio3-thermal site 5 A72 cluster 4 + HSIO3
cluster23-thermal site 6 A72 clusters 2 + 3
Signed-off-by: Vincent Jardin <[email protected]>
Suggested-by: Tom Rini <[email protected]>
Inspired-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the required architecture-specific lookups to enable U-boot SPL to
load images from UFS storage devices on Rockchip RK3576, which has a
boot ROM capable of loading the SPL image from UFS.
Reviewed-by: Jonas Karlman <[email protected]>
Signed-off-by: Alexey Charkov <[email protected]>
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Fix ad-hoc tabs and spaces use, convert to tabs. Drop bogus duplicate
asterisk from non-kerneldoc code comments. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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iMX8MP added 4 new variant parts for low cost industrial and HMI.
The parts disabled HIFI DSP and ISP while other functions are enabled.
Part number:
- MIMX8ML2DVNLZAB and MIMX8ML2CVNKZAB (2-core)
- MIMX8ML5DVNLZAB and MIMX8ML5CVNKZAB (4-core)
Signed-off-by: Ye Li <[email protected]>
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The watchdog base addresses are now obtained from the devicetree via
ofnode_* functions. Remove the hardcoded macro definitions as they are
no longer needed.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Prepare v2026.07-rc3
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Currently mmu_setup for ARMv8 performs two functions, first it sets up
the page tables based the memory map provided by the board and then it
enables the MMU.
However for some platforms runtime fixes to the generated page tables
are required before the MMU can be enabled, such as K3 family of SoCs.
Therefore this patch moves the enablement of the MMU out of mmu_setup
and to a standalone mmu_enable function to give more granular control to
the platforms.
Note that no functional changes are intended from this patch.
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
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DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.
U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.
On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.
Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.
Signed-off-by: Viorel Suman <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Simona Toaca <[email protected]>
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When loading container image, the container header is loaded into
heap memory. If ahab is enabled, the header is be copied to another
fixed RAM for authentication in ahab_auth_cntr_hdr. The better method
is using container header memory being authenticated for following
image loading.
So update ahab_auth_cntr_hdr to return the address of container header
being authenticated. Caller uses this header for following parsing
and image loading.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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When ROM boots from secondary container set, SPL should select
correct offset to load u-boot-atf container.
The implementation uses ROM passover information:
1) For non-eMMC boot partition device, use image offset in ROM
passover data to get u-boot-atf container offset.
2) For eMMC boot partition device, use boot stage (secondary)
in ROM passover data to select correct eMMC boot partition
for u-boot-atf container.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Query the SM via SCMI, obtain rom_passover_t->img_set_sel and based on
that, add 0 or 0x400000 offset (A or B copy offset) to boot container
read address.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Fedor Ross <[email protected]>
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Both consumers and sub-arch specific versions of gpio.h
may reference stdint or other non-C90 type definitions.
Ensure the common ones are available by including linux/types.h
before any other headers.
This issue came to light when the usb onboard hub driver
was enabled for ten64_tfa_defconfig:
In file included from ./arch/arm/include/asm/gpio.h:2,
from common/usb_onboard_hub.c:10:
./arch/arm/include/asm/arch/gpio.h:17:9: error: unknown type name 'ulong'
17 | ulong addr;
./arch/arm/include/asm/arch/gpio.h:18:9: error: unknown type name 'ulong'
18 | ulong size;
./arch/arm/include/asm/arch/gpio.h:19:9: error: unknown type name 'uint'
19 | uint ngpios;
(In this instance, the cited errors actually originate from
arch/arm/include/asm/arch-fsl-layerscape/gpio.h, which is included
by the arm top level asm/gpio.h)
Implemented as per suggestion from Quentin Schulz in Link:
Signed-off-by: Mathew McBride <[email protected]>
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Peng Fan <[email protected]>
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Add an API to check if a specific PSCI function is supported or not.
This is based on the psci_features() function present in Linux kernel
(drivers/firmware/psci/psci.c).
Reviewed-by: Casey Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add configuration for ARMv8-M aarch32 core, which are currently
Cortex-M23/M33 cores. These cores are treated similar to ARMv7-M
cores, except the code has to be compiled with matching compiler
-march=armv8-m.main flag . These cores have no MMU, they have MPU,
which is currently not configured.
Unlike ARMv7-M, these cores have 512 interrupt vectors. While the
SYS_ARM_ARCH should be set to 8, it is set to 7 because all of the
initialization code is built from arch/arm/cpu/armv7m and not armv8.
Furthermore, CONFIG_ARM64 must be disabled, although DTs for devices
using these cores do come from arch/arm64/boot/dts.
To avoid excess duplication in Makefiles, introduce one new Kconfig
symbol, CPU_V7M_V8M. The CPU_V7M_V8M cover both ARMv7-M and ARMv8-M
cores.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Udit Kumar <[email protected]>
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Define CONFIG_SYS_SOC in the mach-sc5xx Kconfig. Follow the standard
U-Boot include path convention by moving the SC5xx SoC headers from
arch/arm/include/asm/arch-adi/sc5xx/ to the conventional
arch/arm/include/asm/arch-sc5xx/ location. Update includes from
<asm/arch-adi/sc5xx/*.h> to <asm/arch/*.h> across mach-sc5xx and board
files.
Signed-off-by: Philip Molloy <[email protected]>
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The ARM32 has PLx Privilege Levels instead of Exception Levels present
on ARM64. Introduce current_pl() function which reports the current PL
on ARM32.
Introduce current_el() for ARM32 as well and current_pl() for ARM64
which each call the other matching function. This is mainly mean to
allow code like this to compile and retain compile time code coverage:
if (IS_ENABLED(CONFIG_ARM64) && current_el() != 3) { ... }
if (!IS_ENABLED(CONFIG_ARM64) && current_pl() != 0) { ... }
Signed-off-by: Marek Vasut <[email protected]>
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Commit bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig)
at least.
The commit message reads
Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
which means ClusterPLL/16
The original submitted patch had the following description:
Value 0xC is reserved. Replace it with correct value 0x5 which
is ClusterPLL/16
Unfortunatly, the little information which was there, was stripped even
further. Why is 0x5 the "correct" value? In fact, it seems that the
upper bit is just ignored and thus the value 0xC translates to 0x4 which
is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL
is clocked at 1.2GHz). But even that is too much for the (default) 03h
read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz.
Link: https://lore.kernel.org/r/[email protected]/
Fixes: bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add definition for Tegra20 SKU 0x4 / A04 found in Sony Tablet P.
Signed-off-by: Ion Agorria <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29557
- Add support for i.MX952.
- Add support for XPI1 on imx943_evk.
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There is a mistmatch between Allwinner's dram_para BSP definitions and the
parameters names in mainline u-boot for TPR1-3. What we call TPR1 is actually
MR22 while TPR2 is TPR0 and TPR3 is TPR1. MR22 does get written to the
corresponding register. This only concerns LPDDR4 support.
Introduce a new Kconfig entry for MR22 and proceed with the rename.
Update the only config currently using it.
See the list of parameters from the Allwinner BSP at the end of:
https://linux-sunxi.org/A133/DRAMC
Note that the H616/H6 code is coherent with this new TPR0 definition
(and does not use TPR1 and MR22).
Signed-off-by: Paul Kocialkowski <[email protected]>
Sponsored-by: MEC Electronics GmbH <https://www.mec.at/>
Acked-by: Jernej Skrabec <[email protected]>
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The XSPI SET GMID command is used to assign GMID ownership to the
requester, allowing access to protected XSPI control registers. This API
must be called in SPL if XSPI GMID-protected settings need to be
modified. Otherwise, XSPI configuration depends on the previous GMID
owner to provide the correct settings.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add CPU type definition and detection macro for i.MX952 SoC.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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System Manager(SM) has implemented the MISC protocol to retrieve DDR
information. Using this API, U-Boot can obtain the DDR size dynamically
instead of relying on static configuration macros.
This change addresses the DDR ECC enabled case, where 1/8 of the total
DDR size is reserved for ECC data. The scmi_misc_ddrinfo() returns the
DDR size with EEC overhead already deducted.
Implementation details:
- Query the DDR size via scmi_misc_ddrinfo()
- Replace direct REG_DDR_CS[0,1]_BNDS register reads with SCMI call
- Switch from PHYS_SDRAM[x]_SIZE macros to runtime detection
- For backward compatibility with older SM firmware, fall back to
static PHYS_SDRAM[x]_SIZE configuration if the SCMI call fails
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-20260316
DFU:
* Make DFU_WRITE_ALT symbol available outside of DFU
* Fix PCI subclass_code warning in spl_dfu
Usb Gadget:
* Mark udc_disconnect() as static
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https://source.denx.de/u-boot/custodians/u-boot-ufs into next
- ufs_hba_ops callbacks cleanup
- Rockchip UFS reset support
- UFS support in SPL
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Add minimal infrastructure to build SPL images with support for UFS
storage devices. This also pulls in SCSI support and charset functions,
which are dependencies of the UFS code.
With this, only a fixed offset is supported for loading the next image,
which should be specified in CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR as the
number of 4096-byte sectors into the UFS block device.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Alexey Charkov <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Rockchip RK3506 is a ARM-based SoC with tri-core Cortex-A7.
Add initial arch support for the RK3506 SoC.
Signed-off-by: Jonas Karlman <[email protected]>
Acked-by: Mattijs Korpershoek <[email protected]> # drivers/usb/gadget
Reviewed-by: Kever Yang <[email protected]>
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Add clock driver for RK3506.
Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
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With the last external callers of udc_disconnect long removed, mark this
function as static now and remove it from headers.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Add missing NAND controller-related clock registers
The NAND controller on H6/H616 uses one clock for its internal logic
(NAND0_CLK) and one clock for ECC engine (NAND1_CLK) in addition to AHB
and MBUS clocks.
As NAND{0,1}_CLKs and MBUS_GATE are missing, add them.
The bit locations are from H616/H6 User Manual.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Some boards feature an "odd" DRAM size, where the total RAM is 1.5GB or
3GB. Our existing DRAM size detection routines can only detect power-of-2
sized configuration, and on those boards the DRAM size is overestimated,
so this typically breaks the boot quite early.
There doesn't seem to be an easy explicit way to detect those odd-sized
chips, but we can test whether the later part of the memory behaves like
memory, by verifying that a written pattern can be read back.
Experiments show that there is no aliasing effect here, as all locations
in the unimplemented range always return some fixed pattern, and cannot
be changed.
Also so far all those boards use a factor of 3 of some lower power-of-2
number, or 3/4th of some higher number. The size detection routine
discovers the higher number, so we can check for some memory cells beyond
75% of the detected size to be legit.
Add a routine the inverts all bits at a given location in memory, and
reads that back to prove that the new value was stored.
Then test the memory cell at exactly 3/4th of the detected size, and cap
the size of the memory to 75% when this test fails. For good measure
also make sure that memory just below the assumed memory end really
works.
This enables boards which ship with such odd memory sizes.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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On GDET enabled part, need to call voltage change start and finish
APIs when adjust the voltage more than 100mv. Otherwise GDET will be
triggered and system is reset
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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