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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: Meenakshi Aggarwal <[email protected]>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
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Update Patrick and my email address with the one dedicated to
upstream activities.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Introduce weak function board_mem_get_layout() which allows overriding
the memory layout from board code in runtime, useful for handling
different SKU versions.
Signed-off-by: Marcel Ziswiler <[email protected]>
Signed-off-by: Igor Opaniuk <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
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The reference design of Allwinner V3 series uses an
AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the
first community-available V3s board, Lichee Pi Zero, omitted it.
Allow to introduce support for the PMIC on boards with it.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- Clock fix MMC driver for SM1 based platforms
- sync SOC Ids from Linux 5.10-rc1
- fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
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These files have a lot of code in common with their counterparts in
coreboot, especially in their earlier revisions:
U-Boot | coreboot
--------------------------------------|--------------------------------------------
drivers/video/rockchip/: | src/soc/rockchip/:
- rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only)
" | - rk3288/display.c (GPL-2.0-only)
" | - rk3399/display.c (GPL-2.0-only)
- rk_hdmi.h (GPL-2.0+) | (none)
- rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later)
- rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later)
- rk3399_hdmi.c (GPL-2.0+) | (none)
- rk_mipi.h (GPL-2.0+) | (none)
- rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only)
- rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only)
- rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only)
- rk_lvds.c (GPL-2.0+) | (none)
- rk_vop.h (GPL-2.0+) | (none)
- rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only)
- rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only)
- rk3399_vop.c (GPL-2.0+) | (none)
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arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*:
- edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only)
" | - rk3288/.../display.h (GPL-2.0-only)
" | - rk3399/.../display.h (GPL-2.0-only)
- vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only)
Restrict the licenses to match coreboot's so that changes from coreboot
can be imported to U-Boot as necessary. HDMI files are already 2.0+
there and rk_lvds.c has no counterpart, so keep them as is.
Cc: Simon Glass <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Cc: Eric Gao <[email protected]>
Cc: Jacob Chen <[email protected]>
Signed-off-by: Alper Nebi Yasak <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang<[email protected]>
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Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h,
remove the useless if/then and fix the meson_gx_mmc.c include.
Signed-off-by: Neil Armstrong <[email protected]>
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- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
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This reverts commit 3a51b2a2c3cedc0d2a9ce981b8e00ab8cefcb6b7.
Signed-off-by: Tom Rini <[email protected]>
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: Razvan Ionut Cirjan <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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- sun8i emac changes (Andre)
- SCP firmware (Samuel)
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This new function, xen_debug_putc(), is intended to be used to
enable CONFIG_DEBUG_UART on xen guest.
Please note that the underlying functionality in Xen is available
only when Xen is configured with !NDEBUG but is much simpler than
a generic HYPERVISOR_console_io().
Signed-off-by: AKASHI Takahiro <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Previously, because we have no source code about the DRAM initialization
of V3s and missing some configurations (delays and MBUS QoS info), our
V3s DRAM initialization sequence is hacked from the H3 one.
As the SDK shipped with PineCube contains source code for V3s libdram,
we can retrieve these information from it and tweak some other magic
bits.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
as its value is IP dependent and not arch dependent
No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops").
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).
Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).
Signed-off-by: Neil Armstrong <[email protected]>
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The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).
But with the G12A family, the USB complex was correctly understood and
implemented correctly.
This adds a proper driver for the glue, based on the G12A one, but with
enough changes to require a different driver in U-Boot.
Signed-off-by: Neil Armstrong <[email protected]>
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Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16
Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.
Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.
Reported-by: Coverity 18045
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2020.10
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- mx6: SOCs user selectable
Fix for imx6q_logic
Some DM conversion
- mx7: introduce secondary boot device
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010
Signed-off-by: Tom Rini <[email protected]>
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- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
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Signed-off-by: Suneel Garapati <[email protected]>
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Signed-off-by: Suneel Garapati <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add 64bit API for clrbits and setbits.
Signed-off-by: Suneel Garapati <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Total Compute is based on ARM architecture and has
the following features enabled in u-boot:
- PL011 UART
- PL180 MMC
- NOR Flash
- FIT image with Signature
- AVB
Signed-off-by: Usama Arif <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP i.MX U-Boot Team <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the user.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP i.MX U-Boot Team <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add the basic differentiation between i.MX6 and i.MX7 into the bmode
command, the mechanism really works almost the same on both platforms.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP i.MX U-Boot Team <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Port hypervisor related code from Mini-OS. This is referencing the code
of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for
ARM64.
Update essential arch code to support required bit operations, memory
barriers etc.
Copyright for the bits ported belong to at least the following authors,
please see related files for details:
Copyright (c) 2002-2003, K A Fraser
Copyright (c) 2005, Grzegorz Milos, [email protected],Intel Research Cambridge
Copyright (c) 2014, Karim Allah Ahmed <[email protected]>
[1] - https://github.com/zyzii/mini-os.git
Signed-off-by: Oleksandr Andrushchenko <[email protected]>
Signed-off-by: Anastasiia Lukianenko <[email protected]>
[trini: Drop wmb() from musb-net/linux-compat.h now]
Signed-off-by: Tom Rini <[email protected]>
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Introduce a minimal Xen guest board running as a virtual
machine under Xen Project's hypervisor [1], [2].
Part of the code is ported from Xen mini-os and also uses
work initially done by different authors from NXP: please see
relevant files for their copyrights.
[1] https://xenbits.xen.org
[2] https://wiki.xenproject.org/
Signed-off-by: Andrii Anisov <[email protected]>
Signed-off-by: Oleksandr Andrushchenko <[email protected]>
Signed-off-by: Anastasiia Lukianenko <[email protected]>
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The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.
Signed-off-by: Chia-Wei, Wang <[email protected]>
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This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Signed-off-by: Simon Glass <[email protected]>
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Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcmns3.
Signed-off-by: Rayagonda Kokatanur <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add API to save boot parameters passed from BL31
Use assembly implementation of save_boot_params instead of c function.
Because generally ATF does not set up SP_EL2 on exiting.
Thus, usage of a C function immediately after exiting with no stack
setup done by ATF explicitly, may cause SP_EL2 to be not sane,
which in turn causes a crash if this boot was not lucky to get
an SP_EL2 in valid range. Replace C implementation with assembly one
which does not use stack this early, and let u-boot to set up its stack
later.
Signed-off-by: Abhishek Shah <[email protected]>
Signed-off-by: Rajesh Ravi <[email protected]>
Signed-off-by: Vladimir Olovyannikov <[email protected]>
Signed-off-by: Rayagonda Kokatanur <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently
defined as no-allocate for both reads and writes, which deviates from the
non-LPAE definition, and mostly defeats the purpose of enabling the caches
in the first place.
So align LPAE with !LPAE, and enable allocate-on-read for both. And while
at it, add some clarification about the meaning of the chosen values.
Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Only the PowerPC architecture needs this function. Remove it.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <[email protected]>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <[email protected]>
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Enable the gpio feature on fsl-layerscape platform.
Signed-off-by: hui.song <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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add one struct mpc8xxx_gpio_plat to enable gpio feature.
Signed-off-by: hui.song <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed.
Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.
So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.
Tested-by: Suniel Mahesh <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.
Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.
However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Rockchip SoC's has a new revision chip for rk3288 SoCs.
RK3288 has a new revision chip called RK3288W which is similar
but different hclk_vio clock and fixed OHCI host.
Add common Rockchip SoC detection helper to support this rk3288w
detection.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.
Signed-off-by: Kever Yang <[email protected]>
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The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:
It's a **mistake** to use typedef for structures and pointers.
Besides, using typedef for structures is annoying when you try to make
headers self-contained.
Let's say you have the following function declaration in a header:
void foo(bd_t *bd);
This is not self-contained since bd_t is not defined.
To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>
#include <asm/u-boot.h>
void foo(bd_t *bd);
Then, the include direcective pulls in more bloat needlessly.
If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:
struct bd_info;
void foo(struct bd_info *bd);
Right, typedef'ing bd_t is a mistake.
I used coccinelle to generate this commit.
The semantic patch that makes this change is as follows:
<smpl>
@@
typedef bd_t;
@@
-bd_t
+struct bd_info
</smpl>
Signed-off-by: Masahiro Yamada <[email protected]>
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Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.
Signed-off-by: Peng Fan <[email protected]>
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