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2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-12-05Remove unused symbolsTom Rini
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-12-05Convert CONFIG_SYS_NS16550_MEM32 et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL. Signed-off-by: Tom Rini <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
2022-11-14Merge tag 'u-boot-imx-20221114' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-11-07ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MPMartyn Welch
The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch <[email protected]>
2022-11-07imx8m: USDHC3 base address definition for i.MX8MPMartyn Welch
The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch <[email protected]>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <[email protected]>
2022-10-24Merge tag 'fsl-qoriq-2022-10-18' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq Layerscape update - support sysreset, - de-select FSL_IFC when booting from SD - disable unused parts of ICID tables - reduce ns_dev size for csu - enable dma snooping for ls104x - nand driver fixups for ls1043ardb rev 7.0 boards.
2022-10-19rockchip: px30: support debug uart on UART0Quentin Schulz
UART0 can obviously also be used for debug uart in U-Boot, so let's add its support. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-10-18arm: layerscape: Disable unused parts of ICID tablesSean Anderson
Several parts of the ICID table are only necessary for U-Boot proper. Disable them in SPL. This saves around 500 bytes. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-10-17arm64: ls104x: Enable eDMA snoopingSean Anderson
This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <[email protected]> Acked-by: Peng Fan <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-10-09imx: gpmi: Add register needed to control nand bus timingMichael Trimarchi
It is used as delay for gpmi write strobe. Signed-off-by: Michael Trimarchi <[email protected]> Reviewed-by: Dario Binacchi <[email protected]> Signed-off-by: Dario Binacchi <[email protected]>
2022-10-06arm: nuvoton: Add support for Nuvoton NPCM845 BMCJim Liu
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <[email protected]>
2022-09-27Merge tag 'u-boot-stm32-20220927' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Increase SYS_MALLOC_F_LEN for STM32 MCU's board - SPL fixes for STM32F7 MCUs - Device tree alignement with kernelv6.0-rc4 for MCU's board - Device tree alignement with kernelv6.0-rc3 for MPU's board - Update DDR node for STM32MP15 - Cleanup config file for STM32MP1 - Update for cmd_stm32key command - Fix compatible string to add partitions for STM32MP1 - Update for stm32programmer tool
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini
into next
2022-09-26configs: stm32f769-disco: Fix internal flash sizePatrice Chotard
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Tested-by: Waldemar Brodkorb <[email protected]>
2022-09-20ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlockMarek Vasut
Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut <[email protected]>
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <[email protected]>
2022-09-18imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVKJesse Taube
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube <[email protected]>
2022-09-13arm: mvebu: Fix moving internal registersPali Rohár
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") moved code from file cpu.c to lowlevel.c, which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE. But the steps describing how to do it correctly were documented only in older U-Boot versions and commit cefd764222ee ("arm: mvebu: Fix internal register config on A38x") probably unintentionally removed important details about MMU from code comments around. Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") implemented code movement according to (now incomplete) comments which resulted in semi-broken code. The result is that I-cache is currently disabled for all Armada 38x boards and maybe there are some other (unreported / undetected) issues. Reimplement it correctly. First flush all caches, then disable MMU and L2 cache and then move Marvell internal registers. There is no need to explicitly disable I-cache. After this change lzmadec command with lzma image of 0x7000000 bytes is doing decompression just 5 seconds. Before this change it was 30 seconds. To make lowlevel.S code more readable, extend asm/pl310.h header file to be compatible with assembler and use macros from this file. Fixes: 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-02Makefile: Allow LTO to be disabled for a buildSimon Glass
LTO (Link-Time Optimisation) is an very useful feature which can significantly reduce the size of U-Boot binaries. So far it has been made available for selected ARM boards and sandbox. However, incremental builds are much slower when LTO is used. For example, an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7 seconds with LTO enabled. Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be disabled during development if needed, for faster builds. Add some documentation about LTO while we are here. Signed-off-by: Simon Glass <[email protected]>
2022-09-02arm: ARMv4 assembly compatibilitySergei Antonov
There is currently a problem that U-Boot can not work on ARMv4 because assembly imlementations of memcpy() and some other functions use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr" should be used instead). A working preprocessor-based solution to this problem is found in arch/arm/lib/relocate.S. Move it to the "ret" macro in arch/arm/include/asm/assembler.h and change all "bx lr" code to "ret lr" in functions that may run on ARMv4. Linux source code deals with this problem in the same manner. v1 -> v2: Comment update. Pointed out by Andre Przywara. Signed-off-by: Sergei Antonov <[email protected]> CC: Samuel Holland <[email protected]> CC: Ye Li <[email protected]> CC: Simon Glass <[email protected]> CC: Andre Przywara <[email protected]> CC: Marek Vasut <[email protected]> CC: Sean Anderson <[email protected]> CC: Tom Rini <[email protected]>
2022-08-20net: lpc32xx_eth.c ethernet driverTom Rini
This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago. Cc: Trevor Woerner <[email protected]> Signed-off-by: Tom Rini <[email protected]> Acked-by: Ramon Fried <[email protected]>
2022-08-12Convert CONFIG_SYS_FSL_QMAN_V3 et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_NGPIXIS CONFIG_SYS_FSL_QMAN_V3 CONFIG_SYS_FSL_RAID_ENGINE CONFIG_SYS_FSL_RMU CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRIO_LIODN CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_USB1_PHY_ENABLE CONFIG_SYS_FSL_USB2_PHY_ENABLE CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY Signed-off-by: Tom Rini <[email protected]>
2022-08-12Convert CONFIG_SYS_FSL_NUM_CC_PLLS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <[email protected]>
2022-08-12Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC Signed-off-by: Tom Rini <[email protected]>
2022-08-12Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et alTom Rini
This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <[email protected]>
2022-08-04Convert CONFIG_SYS_FSL_CORES_PER_CLUSTER to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_CORES_PER_CLUSTER As part of this, correct the dependencies on SYS_FSL_THREADS_PER_CORE. Signed-off-by: Tom Rini <[email protected]>
2022-08-04Convert CONFIG_FSL_MEMAC et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_MEMAC CONFIG_SYS_MEMAC_LITTLE_ENDIAN Signed-off-by: Tom Rini <[email protected]>
2022-08-04Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_CCSR_GUR_BE CONFIG_SYS_FSL_CCSR_SCFG_BE CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_CCSR_GUR_LE CONFIG_SYS_FSL_CCSR_SCFG_LE CONFIG_SYS_FSL_ESDHC_LE CONFIG_SYS_FSL_IFC_LE CONFIG_SYS_FSL_PEX_LUT_LE Signed-off-by: Tom Rini <[email protected]>
2022-08-04Convert CONFIG_SYS_FMAN_V3 to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FMAN_V3 Signed-off-by: Tom Rini <[email protected]>
2022-07-26board: freescale: imx93_evk: support ethernetPeng Fan
Add ethernet support Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx93_evk: Set ARM clock to 1.7GhzPeng Fan
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC to Overdrive voltage 0.9V Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26ddr: imx: Add i.MX9 DDR controller driverYe Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: clock: Add DDR clock supportYe Li
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: Add M33 release prepare functionPeng Fan
To support on-demand booting M33 image from A core. SPL needs to follow M33 kick up sequence to release M33 firstly, then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick M33 to run. The prepare function also works around the M33 TCM ECC issue by clean the TCM. Also enable sentinel handshake and WDOG1 clock for M33 stop and reset. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: Add MIX power initPeng Fan
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation of MIPI DSI/CSI, USBPHY after the power up. SPL should call the power init in its boot sequence before accessing above three MIX and USB. Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: Add gpio registers structureYe Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio driver Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26misc: fuse: support to access fuse on i.MX93Alice Guo
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables for i.MX93. The offset address of FSB accessing OTP shadow registers is different between i.MX8ULP and i.MX93, so use macro to define the offset address instead of hardcode. Signed-off-by: Alice Guo <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msgYe Li
Use more generic name for S40x msg structure Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: Get the chip revision through S400 APIPeng Fan
Update the get chip revision methond to use S400 API, also record other information like lifecycle and UID to global data. Signed-off-by: Peng Fan <[email protected]>
2022-07-26imx: imx9: Add TRDC driver for TRDC initYe Li
Add TRDC driver to iMX9. The TRDC init splits to two phases: 1. Early init phase will release TRDC from Sentinel and open write permission to the memory where SPL image runs. Sentinel will set the memory to RX only after ROM authentication for the OEM closed part. 2. Init phase will configure TRDC to allow non-secure master to access DDR. So the peripherals can work in u-boot. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-07-26misc: s400_api: introduce ahab_release_m33_troutPeng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel release M33 trout and make sure M33 could boot. Signed-off-by: Peng Fan <[email protected]>
2022-07-26misc: S400_API: New API for FW status and chip infoPeng Fan
Add new API to get sentinel FW status and SoC chip info Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-30 12:05:17 +0000