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The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.
To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.
This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.
Signed-off-by: Martin Kaiser <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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In the current H6 CPU memory space code, the SUNXI in the macro name of
the SID address base is wrongly spelled as SNUXI, which leads to SID
readout not working.
Fix this macro name.
Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC")
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
2), set this to 8.
Signed-off-by: Tom Rini <[email protected]>
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Program Central Security Unit (CSU) to grant access to USB 2.0
controller.
Signed-off-by: Ran Wang <[email protected]>
[YS: rewrite commit message]
Reviewed-by: York Sun <[email protected]>
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Move ns_dev[] from header file to C file to avoid compiling warning
when header file is included by others.
Signed-off-by: Ran Wang <[email protected]>
[YS: rewrite commit message]
Reviewed-by: York Sun <[email protected]>
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Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Reviewed-by: Horia Geantă <[email protected]>
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add support for ICID setting of fman ports and the required device
tree fixups.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add a define with a value for the missing debug stream ID.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add defines for the edma and qdma register block base addresses.
Reviewed-by: Bharat Bhushan <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This command is part of the write partition sequence performed by
rkdeveloptool: one partition is first completely erased and
than wrote.
Signed-off-by: Alberto Panizzo <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch implement reading blocks form selected device with
LBA addressing.
Corresponding command on workstation is:
rkdeveloptool rl <start_blk> <blk_cnt> <file>
While we support reading more than one blocks per K_FW_LBA_READ_10
request, rkdeveloptool and original rockchip tool do perform
chunk reads limiting the maximum size per chunk far lower
than max int values.
Signed-off-by: Alberto Panizzo <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.
This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.
The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.
Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.
Add MMC support for H6. EMCE support is not added yet.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).
Add pinmux configuration.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The H6 SoC has a sun6i-style watchdog in its timer part.
Enable the usage of it.
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The new Allwinner H6 SoC has a brand new CCU layout.
Add clock code for it.
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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Allwinner H6 has a different RVBAR address with A64/H5.
Add conditional RVBAR configuration into the code which does RMR switch.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The Allwinner H6 SoC come with a totally new memory map.
Add basical definition of the new memory map into a header file, and let
the cpu.h header include it in the situation of H6.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.
Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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Add a MON_MODE define for ARM's monitor mode. This can be used later by
a secure monitor to avoid hard-coding mode IDs.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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RAM repair has a few pre-requisites:
1) PMIC power supply (rail) enabled.
2) PMC CRAIL power partition powered.
3) Fuse clock active (it's the default).
4) PLLP reshift branch enabled (it's the default, when PLLP is active).
RAM repair also only need run whenever specific partitions are powered
(main SoC and CCPLEX respectively); RAM repair does not need to be
triggered when any other partition changes state.
start_cpu() needs to be re-ordered slightly to match these requirements.
Note that C0NC and CE0 aren't required for RAM repair to
operate, but they also do no harm, so the entire of powerup_cpus() is
moved rather than splitting it up. The call to remove_cpu_resets() is
moved last to ensure that all other actions complete before releasing
reset; since the PMC power partitions are now enabled early, releasing
reset is what causes the CPUs to start executing code, and RAM repair must
complete before the CPU boots.
Note that this commit is the result of squashing a numbmer of commits
in NVIDIA's downstream L4T branch, hence the multiple signoffs below.
Signed-off-by: Bibek Basu <[email protected]>
Signed-off-by: Sandipan Patra <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This reverts commit 701b7b1d2cf657d435d2bd6caf43d0247d37220d. It will
be immediately replaced by a different implementation that is more
complete and runs are more targetted times.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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To get full access of QSPI space, initialize AHB interface.
Signed-off-by: York Sun <[email protected]>
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Remove the old implementation in order to enable DM for sata.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The USBOH module on imx25 chips contains two USB controllers which are
called USB OTG Controller and USB Host Controller. Each one has its EHCI
root hub. The OTG Controller's EHCI registers start at offset 0, the Host
Controller's registers start at offset 0x400.
We set CONFIG_MXC_USB_PORT=0 to select the OTG Controller and 1 for the
Host Controller. Therefore, IMX_USB_PORT_OFFSET must be 0x400. Using
this setting, the Host Controller starts working on my imx25 board.
Please note that the imx25 reference manual claims that the Host
Controller's registers start at 0x200. This is not correct. The Linux
Kernel uses the correct offset 0x400 in imx25.dtsi.
Signed-off-by: Martin Kaiser <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Not all i.MX6 pads use the same drive strength table. So far only the
240 Ohm to 34 Ohm table was available. Because the constants used have
speaking names it can be confusing to use e.g. PAD_CTL_DSE_48ohm when
according to the reference manual 52 Ohm is the correct value. This
patch adds the 260 Ohm to 37 Ohm table.
For example, the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register (SD-card clock)
uses the added table.
Signed-off-by: Mark Jonas <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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This macro allows to detect whether the boot ROM initialized USB
already (serial downloader). This is helpful to reliably detect
if the system has been recovered via USB serial downloader.
Signed-off-by: Stefan Agner <[email protected]>
Acked-by: Marcel Ziswiler <[email protected]>
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Current implementation of find_next_zero_bit() is incompatible with arm64.
Hence fix it by using BITS_PER_LONG define instead of constants and
use generic ffz() implementation.
Signed-off-by: Grygorii Strashko <[email protected]>
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Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
Signed-off-by: Lothar Felten <[email protected]>
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Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <[email protected]>
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This patch update the USB PHY index for Allwinner H3.
Same change[1] initially sent, by 'Chen-Yu Tai' but missed
to apply due to recursive version changes on the same series.
[1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html
Signed-off-by: Jagan Teki <[email protected]>
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Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29
Fixes commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5")
Signed-off-by: Vasily Khoruzhick <[email protected]>
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This undocumented function relies on arch-specific code to declare a nop
weak version. Add the weak function in common code instead to avoid having
to duplicate the same function in each arch.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Alexander Graf <[email protected]>
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This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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ZynqMP emulation platforms are no longer tested and supported that's why
remove macros and code around.
Signed-off-by: Michal Simek <[email protected]>
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Read reset reason reg and show it in log and also save it as variable.
Clearing reset reason when it is read to show only one status
Signed-off-by: Michal Simek <[email protected]>
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Allwinner PHY USB code is now part of generic-phy framework,
so drop existing legacy handling like arch/arm/mach-sunxi.c
and related code areas.
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Jun Nie <[email protected]>
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Clock gating bits on H43/H5 were wrong, fix them.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Acked-by: Jun Nie <[email protected]>
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