| Age | Commit message (Collapse) | Author |
|---|
|
For proper authentication the HAB code must check if the CSF is valid.
Users must call the csf_is_valid() function to parse the CSF prior to
authenticating any additional images. The function will return a failure
if any of the following invalid conditions are met:
- CSF pointer is NULL
- CSF Header does not exist
- CSF does not lie within the image bounds
- CSF command length zero
Signed-off-by: Utkarsh Gupta <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
I/O data lines of UHS SD card operates at 1.8V when in UHS speed
mode (same is true for eMMC in DDR and HS200 modes). Add support
to switch signal voltage to 1.8V in order to support
UHS cards and eMMC HS200 and DDR modes.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
different hw revisions
AM572x SR1.1 requires different IODelay values to be used than that used
in AM572x SR2.0. These values are populated in device tree. Add
capability in omap_hsmmc driver to extract IOdelay values for different
silicon revision. The maximum frequency is also reduced when using a ES1.1.
To keep the ability to boot both revsions with the same dtb, those values
can be provided by the platform code.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
Add a new API to perform iodelay recalibration without isolate
io to be used in uboot.
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met. The MMC driver can use the new API to
set the IO delay values depending on the MMC mode.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.
The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.
The suggested workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
HS200/SDR104 requires tuning command to be sent to the card. Use
the mmc_send_tuning library function to send the tuning
command and configure the internal DLL.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
Use the timing parameter set in the MMC core to set the
mode in UHSMS bit field. This is in preparation for
adding HS200 support in omap hsmmc driver.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
"ti,dual-volt" is used in linux kernel to set the voltage capabilities.
For host controller dt nodes that doesn't have "ti,dual-volt",
it's assumed 1.8v is the io voltage. This is not always true (like in
the case of beagle-x15 where the io lines are connected to 3.3v).
Hence if "no-1-8-v" property is set, io voltage will be set to 3v.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
Add a separate function for starting the clock, stopping the clock and
setting the clock. Starting the clock and stopping the clock can
be used irrespective of setting the clock (For example during iodelay
recalibration).
Also set the clock only if there is a change in frequency.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
|
|
On the NIOS2 and Xtensa architectures, we do not have
CONFIG_SYS_TEXT_BASE set. This is a strict migration of the current
values into the defconfig and removing them from the headers.
I did not attempt to add more default values in and for now will leave
that to maintainers.
Signed-off-by: Tom Rini <[email protected]>
|
|
We should take the MX6DP and MX6QP options in consideration
in the I2C_PADS_INFO macro.
Based on a patch by Pierluigi Passaro <[email protected]>
Signed-off-by: Eran Matityahu <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
We should take the MX6DP and MX6QP options in consideration
when defining imx_iomux_v3_setup_pad().
Based on a patch by Pierluigi Passaro <[email protected]>
Signed-off-by: Eran Matityahu <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
SION bit should be used in the situation that we need
to read back the value of a pin and should not be set by
default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdf
The software input on (SION) bit is an option to force an input
path to be active regardless of the value driven by the
corresponding module. It is used when the nature direction
of a pin depending on selected alternative function is an output,
but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives
the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function
drives the pin and the value is captured by the GPIO
SION bit is not necessary when the pin is configured as a peripheral
apart specific silicon bug. If an application needs to have this
set, this should be done in board file or in dts file
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
Add ddrc memory map and enum types used in ddr initialization.
Signed-off-by: Peng Fan <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Include i.MX8M in lcdif register layout map.
Also included i.MX7ULP in this patch, since share same with i.MX8M.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
Add SoC level initialization code
- arch_cpu_init
- mmu table
- detect cpu revision
- reset cpu and wdog settings
- timer init
- wdog settings
- lowlevel init to save/restore registers
- a few dummy header file to avoid build failure
- ft_system_setup
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
|
|
Move get_boot_device to cpu.c to prepare adding i.MX8M support,
because i.MX8M share same code with i.MX7.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Move i.MX6/7 bootaux code to imx_bootaux.c.
The i.MX6/7 has different src layout, so define M4 reg offset
to ease the cleanup. Redefine the M4 related BIT for share
common code.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
|
|
Add pad settings bit definition for i.MX8M.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Add USB_BOOT entry.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
Add SiP (Silicon Provider) services function to issue
SMC call to Arm Trusted Firmware.
More SiP information could be found in
https://github.com/ARM-software/arm-trusted-firmware/blob/master/
docs/arm-sip-service.rst
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Add clock driver to support i.MX8M.
There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.
Signed-off-by: Peng Fan <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Add pin header file for i.MX8M
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Add register definition header file for i.MX8M
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Xilinx changes for v2018.03
- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates
- ZynqMP psu rework based on Zynq concept
- Add low level initialization for zc770 and zcu102
- Add support for Zynq zc770 x16 nand configuration
- Add mini nand/emmc ZynqMP targets
- Some arasan nand changes
|
|
Move generic functions to common location psu_spl_init.c. Function
declarations are added to private header.
These changes are done in connection to the fact that still files from
HDF can be copied over and compilation should pass.
Signed-off-by: Michal Simek <[email protected]>
|
|
psu_init() returns int which wasn't declared and checked.
The patch is fixing function declarations and code to handle return
values properly.
Signed-off-by: Michal Simek <[email protected]>
|
|
|
|
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
|
|
Move SYSCFG clock setup into configure_clocks() instead of calling
clock_setup() from board file.
As this clock is only needed in case of ethernet enabled and as
both stm32f4 and stm32f7 are using the Designware ethernet IP,
we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed.
Move the RMII setup from board_early_init_f() to board_init()
to insure that RMII bit is set only when clock driver is initialized.
Signed-off-by: Patrice Chotard <[email protected]>
|
|
Thanks to 'commit ba1f96672522 ("net: designware: add clock support")'
we don't need anymore to setup the STMMAC clock in board.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
|
|
|
|
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.
Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Restructures common driver to support LTC3882 voltage regulator
chip.
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Update prcm, voltages and pinmux support for am574x-idk.
Signed-off-by: Lokesh Vutla <[email protected]>
|
|
DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR@1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs
Both the above packages uses the same IDCODE hence needs to
differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.
Signed-off-by: Lokesh Vutla <[email protected]>
|
|
Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7 platforms.
Signed-off-by: Lokesh Vutla <[email protected]>
|
|
For data integrity, the EMIF1 supports ECC on the data
written or read from the SDRAM. Add support for enabling
ECC support in EMIF1.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Krunal Bhargav <[email protected]>
|
|
This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.
Signed-off-by: Lokesh Vutla <[email protected]>
|
|
Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.
Signed-off-by: Tero Kristo <[email protected]>
|
|
MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance
to use if any at all is done through
CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is
handled in U-boot. Handle this additional pinmuxing requirement in U-boot
to ensure that MCAN is used by default via the DCAN1 pins.
Reviewed-by: Lokesh Vutla <[email protected]>
Signed-off-by: Vignesh R <[email protected]>
[[email protected]: Update commit message and use DCAN1 not DCAN2 for MCAN]
Signed-off-by: Franklin S Cooper Jr <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Faiz Abbas <[email protected]>
|
