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The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.
This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never
power off the usb ports")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Move this option to Kconfig and tidy up existing uses.
Signed-off-by: Simon Glass <[email protected]>
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Move this option to Kconfig and tidy up existing uses.
Signed-off-by: Simon Glass <[email protected]>
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Move this option to Kconfig and tidy up existing uses.
Signed-off-by: Simon Glass <[email protected]>
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A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Signed-off-by: Simon Glass <[email protected]>
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A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Note that quite a few boards defined this options but do not appear to
actually use SPL:
BSC9132QDS_NOR_DDRCLK100_SECURE
BSC9132QDS_NOR_DDRCLK133_SECURE
BSC9132QDS_SDCARD_DDRCLK100_SECURE
BSC9132QDS_SDCARD_DDRCLK133_SECURE
BSC9132QDS_SPIFLASH_DDRCLK100_SECURE
BSC9132QDS_SPIFLASH_DDRCLK133_SECURE
C29XPCIE_NOR_SECBOOT
P1010RDB-PA_36BIT_NAND_SECBOOT
P1010RDB-PA_36BIT_SPIFLASH_SECBOOT
P1010RDB-PA_NAND_SECBOOT
P1010RDB-PA_NOR_SECBOOT
P1010RDB-PB_36BIT_NOR_SECBOOT
P1010RDB-PB_36BIT_SPIFLASH_SECBOOT
P1010RDB-PB_NAND_SECBOOT
P1010RDB-PB_NOR_SECBOOT
P3041DS_SECURE_BOOT
P4080DS_SECURE_BOOT
P5020DS_NAND_SECURE_BOOT
P5040DS_SECURE_BOOT
T1023RDB_SECURE_BOOT
T1024QDS_DDR4_SECURE_BOOT
T1024QDS_SECURE_BOOT
T1024RDB_SECURE_BOOT
T1040RDB_SECURE_BOOT
T1042D4RDB_SECURE_BOOT
T1042RDB_SECURE_BOOT
T2080QDS_SECURE_BOOT
T2080RDB_SECURE_BOOT
T4160QDS_SECURE_BOOT
T4240QDS_SECURE_BOOT
ls1021aqds_nor_SECURE_BOOT
ls1021atwr_nor_SECURE_BOOT
ls1043ardb_SECURE_BOOT
For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since
they apparently don't have an SPL, this should not matter.
Signed-off-by: Simon Glass <[email protected]>
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The secure boot header files incorrectly define SPL options only if
CONFIG_SPL_BUILD is defined. This means that the options are only enabled
in an SPL build, and not with a normal 'make xxx_defconfig'. This means
that moveconfig.py cannot work, since it sees the options as disabled even
when they may be manually enabled in an SPL build.
Fix this by changing the order.
Signed-off-by: Simon Glass <[email protected]>
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Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch adds definitions of all the regesters necessary for
system sleep.
Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Debug server feature has been dropped from roadmap.
Signed-off-by: York Sun <[email protected]>
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As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: York Sun <[email protected]>
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On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area. As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow. As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.
Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
Cc: Albert Aribaud <[email protected]>
Cc: Nagendra T S <[email protected]>
Cc: Vaibhav Hiremath <[email protected]>
Cc: Lokesh Vutla <[email protected]>
Cc: Felipe Balbi <[email protected]>
Cc: Igor Grinberg <[email protected]>
Cc: Nikita Kiryanov <[email protected]>
Cc: Paul Kocialkowski <[email protected]>
Cc: Enric Balletbo i Serra <[email protected]>
Cc: Adam Ford <[email protected]>
Cc: Steve Sakoman <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Thomas Weber <[email protected]>
Cc: Hannes Schmelzer <[email protected]>
Cc: Thomas Chou <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sam Protsenko <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Samuel Egli <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Mateusz Kulikowski <[email protected]>
Cc: Ben Whitten <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Sekhar Nori <[email protected]>
Cc: Mugunthan V N <[email protected]>
Cc: "B, Ravi" <[email protected]>
Cc: "Matwey V. Kornilov" <[email protected]>
Cc: Ladislav Michl <[email protected]>
Cc: Ash Charles <[email protected]>
Cc: "Kipisz, Steven" <[email protected]>
Cc: Daniel Allred <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Tested-by: Lokesh Vutla <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Tested-by: Ladislav Michl <[email protected]>
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Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Eric Nelson <[email protected]>
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This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Luka Perkov <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nagendra T S <[email protected]>
Cc: Vaibhav Hiremath <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Cc: Steve Rae <[email protected]>
Cc: Igor Grinberg <[email protected]>
Cc: Nikita Kiryanov <[email protected]>
Cc: Stefan Agner <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Cc: Mateusz Kulikowski <[email protected]>
Cc: Peter Griffin <[email protected]>
Acked-by: Paul Kocialkowski <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Acked-by: "Pali Rohár" <[email protected]>
Cc: Adam Ford <[email protected]>
Cc: Steve Sakoman <[email protected]>
Cc: Grazvydas Ignotas <[email protected]>
Cc: Nishanth Menon <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Robert Baldyga <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Thomas Weber <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: David Feng <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: York Sun <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Prabhakar Kushwaha <[email protected]>
Cc: Aneesh Bansal <[email protected]>
Cc: Saksham Jain <[email protected]>
Cc: Qianyu Gong <[email protected]>
Cc: Wang Dongsheng <[email protected]>
Cc: Alex Porosanu <[email protected]>
Cc: Hongbo Zhang <[email protected]>
Cc: tang yuantian <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Cc: Josh Wu <[email protected]>
Cc: Bo Shen <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: Hannes Schmelzer <[email protected]>
Cc: Thomas Chou <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sam Protsenko <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Christophe Ricard <[email protected]>
Cc: Anand Moon <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Carlo Caione <[email protected]>
Cc: huang lin <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Xu Ziyuan <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: "Ariel D'Alessandro" <[email protected]>
Cc: Kever Yang <[email protected]>
Cc: Samuel Egli <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Hans de Goede <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Siarhei Siamashka <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Andre Przywara <[email protected]>
Cc: Bernhard Nortmann <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Ben Whitten <[email protected]>
Cc: Tom Warren <[email protected]>
Cc: Alexander Graf <[email protected]>
Cc: Sekhar Nori <[email protected]>
Cc: Vitaly Andrianov <[email protected]>
Cc: "Andrew F. Davis" <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Carlos Hernandez <[email protected]>
Cc: Ladislav Michl <[email protected]>
Cc: Ash Charles <[email protected]>
Cc: Mugunthan V N <[email protected]>
Cc: Daniel Allred <[email protected]>
Cc: Gong Qianyu <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Masahiro Yamada <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Paul Kocialkowski <[email protected]>
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The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.
The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".
An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <[email protected]>
Reviewed by: Peter Korsgaard <[email protected]>
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[trini: Drop CMD_BOOTI as it's now on by default on ARM64]
Signed-off-by: Tom Rini <[email protected]>
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Move form arch/arm/include/asm/arch-rmobile/ to arch/arm/mach-rmobile/include/mach/.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system. Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.
Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.
I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable. However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.
CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.
Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada <[email protected]>
Reported-by: Ravi Babu <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Ziyuan Xu <[email protected]>
Acked-by: Sandy Patterson <[email protected]>
Reported-by: Ziyuan Xu <[email protected]>
Reported-by: Sandy Patterson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.
Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.
Signed-off-by: Wang Dongsheng <[email protected]>
Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <[email protected]>
Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <[email protected]>
Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <[email protected]>
Signed-off-by: Wang Dongsheng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Mihai Bantea <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.
Reviewed-by: Aneesh Bansal <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.
Reviewed-by: Aneesh Bansal <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.
[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The register offset of i2c_sysc offset is not correct as per
omap4 TRM [1], correct the offsets as per the documentation.
[1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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