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Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.
When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add more entries for structure mxc_ccm_reg.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Eric Nelson <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update GPMI NAND driver and BCH head file to support i.MX7
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update APBH-DMA driver and head files to support i.MX7D
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <[email protected]>
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These work reasonable well, but there are a few errors:
- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also
Signed-off-by: Simon Glass <[email protected]>
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Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Signed-off-by: Simon Glass <[email protected]>
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Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.
Signed-off-by: Simon Glass <[email protected]>
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Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.
Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Signed-off-by: Simon Glass <[email protected]>
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These should match the datasheet naming. Adjust them.
Signed-off-by: Simon Glass <[email protected]>
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Add a simple driver which implements the standard PWM uclass interface.
Signed-off-by: Simon Glass <[email protected]>
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The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.
Signed-off-by: Simon Glass <[email protected]>
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This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.
Adjust it, adding an enum to improve readability.
Signed-off-by: Simon Glass <[email protected]>
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Signed-off-by: Jelle van der Waa <[email protected]>
[[email protected]: Minor cleanups]
Signed-off-by: Hans de Goede <[email protected]>
applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs
Signed-off-by: Heiko Schocher <[email protected]>
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compiling U-Boot for openrd_base_defconfig with
gcc 5.x shows the following warning:
CC fs/ubifs/super.o
In file included from fs/ubifs/ubifs.h:35:0,
from fs/ubifs/super.c:37:
fs/ubifs/super.c: In function 'atomic_inc':
./arch/arm/include/asm/atomic.h:55:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
local_irq_save(flags);
^
fs/ubifs/super.c: In function 'atomic_dec':
./arch/arm/include/asm/atomic.h:64:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
local_irq_save(flags);
^
CC fs/ubifs/sb.o
[...]
CC fs/ubifs/lpt.o
In file included from include/linux/bitops.h:123:0,
from include/common.h:20,
from include/ubi_uboot.h:17,
from fs/ubifs/ubifs.h:37,
from fs/ubifs/lpt.c:35:
fs/ubifs/lpt.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
local_irq_save(flags);
^
CC fs/ubifs/lpt_commit.o
In file included from include/linux/bitops.h:123:0,
from include/common.h:20,
from include/ubi_uboot.h:17,
from fs/ubifs/ubifs.h:37,
from fs/ubifs/lpt_commit.c:26:
fs/ubifs/lpt_commit.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
local_irq_save(flags);
^
CC fs/ubifs/scan.o
CC fs/ubifs/lprops.o
CC fs/ubifs/tnc.o
In file included from include/linux/bitops.h:123:0,
from include/common.h:20,
from include/ubi_uboot.h:17,
from fs/ubifs/ubifs.h:37,
from fs/ubifs/tnc.c:30:
fs/ubifs/tnc.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
local_irq_save(flags);
^
CC fs/ubifs/tnc_misc.o
Fix it.
Signed-off-by: Heiko Schocher <[email protected]>
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This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this
Signed-off-by: Sergey Temerkhanov <[email protected]>
Signed-off-by: Corey Minyard <[email protected]>
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Mateusz Kulikowski <[email protected]>
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This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov <[email protected]>
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
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This patch adds the read_mpidr() function which returns the
MPIDR_EL1 register value
Signed-off-by: Sergey Temerkhanov <[email protected]>
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <[email protected]>
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For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.
Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.
The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.
For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.
The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.
For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.
Example:
void mxs_power_setup_dcdc_clocksource(void)
{
mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}
Signed-off-by: Michael Heimpold <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Mingkai Hu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <[email protected]>
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This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Kamil Lulko <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.
Signed-off-by: Vishnu Patekar <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <[email protected]>
[[email protected]] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[[email protected]] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <[email protected]>
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On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
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Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:
"
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
}
"
Without this patch, we will always encounter "Wrong LCD interface".
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Move driver to DM
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove unused macros when driver was moved to DM.
Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Kamil Lulko <[email protected]>
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add rk3036 sdram driver so we can set up sdram in SPL
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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add early uart driver so we can print debug message in
SPL stage
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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GRF is the gereral register file. Add header files with register definitions.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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