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This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.
Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.
Signed-off-by: Albert ARIBAUD <[email protected]>
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Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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This is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Chan-Taek Park <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Po-Yu Chuang <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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These are still non-generic boards.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Greg Ungerer <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Lei Wen <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Matthias Weisser <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.
Signed-off-by: Xiubo Li <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Minghuan Lian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.
VA mapping:
------- <---- 0GB
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|-------| <---- 0x24000000
|///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
|-------| <---- 0x300000000
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|-------| <---- 0x34000000
|///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
|-------| <---- 0x40000000
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|-------| <---- 0x80000000 DDR0 space start
|\\\\\\\|
|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
|\\\\\\\|
------- <---- 4GB DDR0 space end
Signed-off-by: Minghuan Lian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch is to define default values for some CCSR macros
to make header files cleaner.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Erratum A008514 appleis to ls2085a.
Signed-off-by: York Sun <[email protected]>
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Erratum A008336 applied to LS2085A.
Signed-off-by: York Sun <[email protected]>
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FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <[email protected]>
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Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun <[email protected]>
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Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.
Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.
Signed-off-by: York Sun <[email protected]>
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According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun <[email protected]>
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This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.
The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.
Signed-off-by: Bhupesh Sharma <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This adds the DATA[4-7] and RST pin definitions.
Signed-off-by: Otavio Salvador <[email protected]>
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A few pad settings are I2C1
Signed-off-by: Peng Fan <[email protected]>
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Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
halving the mbus frequency, so set it to 300 MHz ourselves and base the
mbus divider on that.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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USB doesn't seem to work yet; the controller detects the on-board Hub/
Ethernet device but can't read the descriptors from it. I haven't
investigated yet.
Signed-off-by: Stephen Warren <[email protected]>
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The bcm2835 and bcm2836 are essentially identical, except:
- The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
- The physical address of many IO controllers has moved.
Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
update the existing bcm2835 code to handle the minor differences, and
plumb it into the ARMv7 CPU architecture.
Signed-off-by: Stephen Warren <[email protected]>
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Signed-off-by: Stephen Warren <[email protected]>
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Move arch/arm/include/asm/arch-keystone/*
-> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
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Move arch/arm/include/asm/arch-orion5x/*
-> arch/arm/mach-orion5x/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
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Move arch/arm/include/asm/arch-nomadik/*
-> arch/arm/mach-nomadik/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Nomadik Linux Team <[email protected]>
Cc: Alessandro Rubini <[email protected]>
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Move arch/arm/include/asm/arch-kirkwood/*
-> arch/arm/mach-kirkwood/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Luka Perkov <[email protected]>
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Move arch/arm/include/asm/arch-davinci/*
-> arch/arm/mach-davinci/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
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Move arch/arm/include/asm/arch-at91/*
-> arch/arm/mach-at91/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Eric Nelson <[email protected]>
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The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ranjani Vaidyanathan <[email protected]>
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The only LPC3250 board works fine with enabled generic board support,
add CONFIG_SYS_GENERIC_BOARD right into the arch config header.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
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Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of
creating its own. There are some #ifdefs required in start.S. Future work
will hopefully remove these.
This series is available at u-boot-dm, branch sunxi-working.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Some boards have a special way of loading U-Boot that does not fit with
the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot
is loaded over USB. Add a CONFIG option and boot mode for this.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Siarhei Siamashka <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The link register value can be required on some boards (e.g. FEL mode on
sunxi) so use a branch instruction to jump to save_boot_params() instead
of a branch link.
This requires a branch back to save_boot_params_ret so adjust the users
to deal with this. For exynos just drop the function since it doesn't
do anything.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Siarhei Siamashka <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Move the dram helper functions to a separate C file, rather then having them
as inline helpers in dram.h. This saves 144 bytes in the .text segment for
sun6i builds.
Signed-off-by: Hans de Goede <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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KS2 ddr3 initialization uses ddr3_size global variable before u-boot
relocation. Even if the variable is not being used after relocation,
writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one
instead.
Signed-off-by: Vitaly Andrianov <[email protected]>
Tested-by: Nishanth Menon <[email protected]>
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When EMAC is in the boot order, the boot ROM sets OPP50 and the
MAC clock is set to /2. SPL needs to change it to /5 for Ethernet
to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz <[email protected]>
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The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <[email protected]>
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We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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