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Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.
Signed-off-by: Luc Verhaegen <[email protected]>
[[email protected]: Use pre-populated simplefb node under /chosen as
disussed on the devicetree list]
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>.
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This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.
This code is enabled when HPD detects an attached monitor.
Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.
cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.
Signed-off-by: Luc Verhaegen <[email protected]>
[[email protected]: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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This is a preparation patch for adding support for HDMI out.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.
Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31
This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Minghuan Lian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Conflicts:
drivers/serial/serial-uclass.c
Signed-off-by: Tom Rini <[email protected]>
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Implement disable_sata_clock for mx6 SoCs.
Signed-off-by: Nikita Kiryanov <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Nitin Garg <[email protected]>
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Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver model
as well as those that have not.
Signed-off-by: Simon Glass <[email protected]>
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These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs which are no longer
required.
Signed-off-by: Simon Glass <[email protected]>
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Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.
Signed-off-by: Simon Glass <[email protected]>
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CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.
Signed-off-by: Masahiro Yamada <[email protected]>
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CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM920T and replaces the
only reference in drivers/usb/host/ohci-hcd.c with CONFIG_CPU_ARM920T.
Signed-off-by: Masahiro Yamada <[email protected]>
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Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Fabio Estevam <[email protected]>
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Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.
Signed-off-by: Fabio Estevam <[email protected]>
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There are 8 SCFG_SPARECR registers in SCFG memory block, not one.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <[email protected]>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <[email protected]>
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The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Bo Shen <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
[adopt Bo's change in spl.c]
Signed-off-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.
Signed-off-by: Suriyan Ramasami <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Enable/disable the usb host phy on the odroid U/X2 boards which are based
on the Exynos4412 SOC.
Signed-off-by: Suriyan Ramasami <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
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Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.
Signed-off-by: Thierry Reding <[email protected]>
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The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code. This commit adds a simple
macro that is available in asm code.
Signed-off-by: Masahiro Yamada <[email protected]>
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Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).
TODO for me:
Move the base address to device trees.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This commit adds register defines of MIO (Media I/O) block
of UniPhier platform. This file is necessary to control
the reset signals of the USB cores.
Signed-off-by: Masahiro Yamada <[email protected]>
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R-Car SoCs of rmobile have same IP of rcar-i2c, and have same address.
This moves rcar-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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R-Car SoCs of rmobile have same IP of sh-i2c, and have same address.
This moves sh-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs, and headers of each SoCs.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.
Signed-off-by: Hisashi Nakamura <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.
This function is called from arch_early_init_r() if the SPI
driver is enabled.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Pavel Machek <[email protected]>
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This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.
Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.
Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Simon Glass <[email protected]>
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