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Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this
function weak.
In addition open code the trivial and useless BOARD_REV_ID define and
adjust the comment.
Signed-off-by: Igor Grinberg <[email protected]>
Cc: Tom Rini <[email protected]>
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The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.
Acked-by: Murali Karicheri <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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Keystone2 Lamar SoC uses the same keystone SerDes driver.
All Keystone2 EVM boards currently use SerDes driver, so move
CONFIG_TI_KEYSTONE_SERDES to common configuration file.
Acked-by: Murali Karicheri <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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The Keystone2 Lamar SoC uses the same keystone navigator.
Move queue numbers to common hardware file, as all Keystone2 SoCs
have the same ones.
Acked-by: Murali Karicheri <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Mostly automatic with:
sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.
Signed-off-by: Ian Campbell <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.
Signed-off-by: Hisashi Nakamura <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.
Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.
The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.
Signed-off-by: Ye.Li <[email protected]>
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Set the USDHC1-3 IOMUX settings which are used for mx6slevk board.
Signed-off-by: Ye.Li <[email protected]>
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The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCM
Signed-off-by: Ye.Li <[email protected]>
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[1] arch/arm/include/asm/arch-at91/at91_shdwn.h
The top9000 was the last board to use this header file.
It was removed by commit d58a9451e733 (ppc/arm: zap EMK boards).
[2] board/matrix_vision/common/*
Some Matrix Vision boards were dropped by commit e7a565638a7a
(powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7)
and commit af55e35d3389
(powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR).
Since then these files have been unused.
[3] include/usb/omap1510_udc.h
The omap5912osk was the last board to use this header file.
It was removed by commit 62d636aa2ac2
(omap: remove omap5912osk board support).
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-By: Wolfgang Denk <[email protected]>
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fix typos in video pll related register names and bit defines
Signed-off-by: Soeren Moch <[email protected]>
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This patch adds extra gpio part addresses to exynos4
and exynos4x12_gpio_data arrays, which are required
since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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After remove the offsets in Exynos4/4x12 gpio enums,
an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Fix name for Video PLL denominator register.
Signed-off-by: Anatolij Gustschin <[email protected]>
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a hexadicemal value was missing the "0x" prefix which caused
assembler error
Signed-off-by: Yehuda Yitschak <[email protected]>
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Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Albert Aribaud <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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U-Boot does not have arch/arm/kernel, include/uapi directories,
This commit copies files as follows:
Location in Linux -> Location in U-Boot
arch/arm/kernel/debug.S -> arch/arm/lib/debug.S
arch/arm/include/debug/8250.S -> arch/arm/include/debug/8250.S
include/uapi/linux/serial_reg.h -> include/linux/serial_reg.h
Signed-off-by: Masahiro Yamada <[email protected]>
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Fix a trivial conflict over adding <dm.h>
Conflicts:
arch/arm/cpu/armv7/omap3/board.c
Signed-off-by: Tom Rini <[email protected]>
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while at it, fix a typo
Signed-off-by: Jeroen Hofstee <[email protected]>
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Signed-off-by: Jeroen Hofstee <[email protected]>
Acked-by: Albert ARIBAUD <[email protected]>
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Signed-off-by: Jeroen Hofstee <[email protected]>
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mxs_wait_mask_set and friends need a declaration
of struct mxs_register_32.
Signed-off-by: Jeroen Hofstee <[email protected]>
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This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede <[email protected]>
[[email protected]: expanded commit message]
[[email protected]: add pin bank M and expand comments]
[[email protected]: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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UART0 pin muxes on the A23 have a different function value.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The watchdog on sun6i/sun8i has a different layout.
Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
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The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.
Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.
Move the register definitions to a separate file to facilitate
supporting newer SoCs.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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UART0 is the default debug/console UART on the A31.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.
Signed-off-by: Hans de Goede <[email protected]>
[[email protected]: use setbits_le32 for reset control, drop obsolete changes,
rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
This includes changes from the following commits from u-boot-sunxi:
a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
[[email protected]: styling fixes reported by checkpatch.pl]
[[email protected]: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Cc: Tom Cubie <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.
This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
[[email protected]: spacing fixes reported by checkpatch.pl]
[[email protected]: Use setbits helper in PRCM init function]
[[email protected]: rephrase commit message to explain what the hardware
supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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This commit converts UniPhier on-chip serial driver to driver model.
Since UniPhier SoCs do not have Device Tree support, some board files
should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories.
(Device Tree support for UniPhier platform is still under way.)
Now the base address and master clock frequency are passed from
platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and
CONFIG_SYS_UNIPHIER_UART_CLK should be removed.
Tested on UniPhier PH1-LD4 ref board.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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