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This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Inki Dae <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc
in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic
usase of tzpc.
Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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DM3730 needs some additional pin mux configuration for GPIOs
126-129 to work, add it.
Signed-off-by: Grazvydas Ignotas <[email protected]>
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Avoid using __attribute__ ((__packed__)) unless it's
absolutely necessary. "packed" will remove alignment
requirements for the respective objects and may cause
alignment issues unless alignment is also enforced
using a pragma.
Here, these packed attributes were causing alignment
faults in Thumb build.
Signed-off-by: Aneesh V <[email protected]>
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This will add ARM specific over-rides for the defines
from linux/linkage.h
Signed-off-by: Aneesh V <[email protected]>
Tested-by: Mike Frysinger <[email protected]>
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The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: R Sricharan <[email protected]>
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Add omap5 pbias configuration for mmc1/sd lines
and set voltage for sd data i/o lines
Signed-off-by: Balaji T K <[email protected]>
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In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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PD_TIM bit field which specifies the power down timing is defined
to occupy bits 8-11, where as it is actually from 12-15 bits.
So correcting this.
Signed-off-by: R Sricharan <[email protected]>
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Add support to identify the device as GP/EMU/HS.
Signed-off-by: R Sricharan <[email protected]>
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Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.
Signed-off-by: R Sricharan <[email protected]>
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The full internal SRAM of size 128kb is public in the case of OMAP5 soc.
So change the base address accordingly.
Signed-off-by: R Sricharan <[email protected]>
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The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.
Signed-off-by: R Sricharan <[email protected]>
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The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <[email protected]>
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The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <[email protected]>
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The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.
Signed-off-by: R Sricharan <[email protected]>
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Adding the full pinmux data for OMAP5430 sevm board.
Signed-off-by: R Sricharan <[email protected]>
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Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.
Signed-off-by: R Sricharan <[email protected]>
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TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <[email protected]>
Reported-by: Jerome Angeloni <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
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OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.
With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.
NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.
Reported-by: Isabelle Gros <[email protected]>
Reported-by: Jerome Angeloni <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
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Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.
Signed-off-by: Jonathan Solnit <[email protected]>
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This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This change adds initial support for NXP LPC32x0 SoC series.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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In driver mmc, generic s5p_sdhci code is implemented.
s5p_mmc file is dupulicated.
we are good that use the generic sdhci.
This patch supported the sdhci for Samsung-SoC.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Lei Wen<[email protected]>
Acked-by: Minkyu Kang <[email protected]>
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Earlier, a driver exists in the u-boot source for designware i2c interface. That
driver was specific to spear platforms. This patch implements the i2c controller
as a generic driver which can be used by multiple platforms
The driver files are now renamed to designware_i2c.c and designware_i2c.h and
these are moved into drivers/i2c folder for reusability by other
platforms
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
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This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.
The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.
The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.
NOTE: This patch depends on:
http://patchwork.ozlabs.org/patch/150957/
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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Remove gpio related unused/repititive definitions from imx headers.
Signed-off-by: Vikram Narayanan <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Eric Nelson <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Add basic i2c driver for Tegra2 with 8- and 16-bit address support.
The driver requires CONFIG_OF_CONTROL to obtain its configuration
from the device tree.
(Simon Glass: [email protected] modified for upstream)
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC).
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Adds prep subcommand to bootm implementation of ARM. When bootm is called
with the subcommand prep the function stops right after ATAGS creation and
before announce_and_cleanup.
This is used in command "cmd_spl export"
Signed-off-by: Simon Schwarz <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This adds Linux booting to the SPL
This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)
Related CONFIGs:
CONFIG_SPL_OS_BOOT
Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
defines the IO-pin number u-boot switch - if pressed u-boot is
booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normaly RAM-begin + 0x100
Signed-off-by: Simon Schwarz <[email protected]>
CC: Tom Rini <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Wolfgang Denk <[email protected]>
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Linux crashes if the GPMC isn't configured for the dm9000.
Signed-off-by: Simon Schwarz <[email protected]>
CC: Tom Rini <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Wolfgang Denk <[email protected]>
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Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Jason Liu <[email protected]>
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Remove duplicate definition of ANATOP_BASE_ADDR.
Signed-off-by: Fabio Estevam <[email protected]>
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The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7.
This is due to the fact that there are two registers for total of 16 lines.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bryan Hundven <[email protected]>
Cc: Michael Schwingen <[email protected]>
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Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.
Signed-off-by: Matt Porter <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
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This patch introduces an 8-bit register, mx28_register_8, in order to
prepare for fixing erroneous 32-bit wide access of registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
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This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by: Robert Delien <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
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Currently, only USB Host 1 is supported.
Cc: Remy Bohmer <[email protected]>
Signed-off-by: Wolfgang Grandegger <[email protected]>
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This patch adds register definitions for the registers of the DIGCTL
IP-block.
Signed-off-by: Robert Delien <[email protected]>
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This patch adds support for USB EHCI driver for Armada100 SOCs.
Signed-off-by: Ajay Bhargav <[email protected]>
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This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.
Signed-off-by: Ajay Bhargav <[email protected]>
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The video setup for the Epson display is provided. Addtionally
some extra info is displayed next to the Linux logo.
Make get_cpu_rev() publicly available (added to sys_proto.h).
Signed-off-by: Helmut Raiger <[email protected]>
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Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Dirk Behme <[email protected]>
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