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Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai <[email protected]>
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Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Signed-off-by: Horia Geantă <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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There are no platforms for this architecture anymore, remove unused
code.
Signed-off-by: Tom Rini <[email protected]>
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A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.
The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
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H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.
Signed-off-by: Angelo Dureghello <[email protected]>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <[email protected]>
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SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Create a do-nothing driver for each sunxi pin controller variant.
Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This imports some defines for esr and spsr from Linux v5.16. I have
modified the includes and fixed some indentation nits but otherwise it
is the same. There are a lot more defines than we need, but it doesn't
hurt.
Signed-off-by: Sean Anderson <[email protected]>
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This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.
Signed-off-by: Sean Anderson <[email protected]>
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To avoid passing around an extra register everywhere, save esr in
pt_regs like the rest. For proper alignment we need to have a second
(unused) register. All the printfs have to be adjusted, since
it's now an unsigned long and not an int.
Signed-off-by: Sean Anderson <[email protected]>
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This adds a boot method for loading the next stage from the host. It is
mostly modeled off of spl_load_image_ext. I am not really sure why/how
spl_load_image_fat uses three different methods to load the image, but
the simple case seems to work OK for now.
To control the presence of this boot method, we add a config symbol.
While we're at it, we update the original semihosting config symbol.
I think semihosting has some advantages of other forms of JTAG boot.
Common other ways to boot from JTAG include:
- Implementing DDR initialization through JTAG (typically with dozens of
lines of TCL) and then loading U-Boot. The DDR initialization
typically uses hard-coded register writes, and is not easily adapted
to different boards. BOOT_DEVICE_SMH allows booting with SPL,
leveraging U-Boot's existing DDR initialization code. This is the
method used by NXP's CodeWarrior IDE on Layerscape processors (see
AN12270).
- Loading a bootloader into SDRAM, waiting for it to initialize DDR, and
then loading U-Boot. This is tricky, because the debugger must stop the
boot after the bootloader has completed its work. Trying to load
U-Boot too early can cause failure to boot. This is the method used by
Xilinx with its Zynq(MP) processors.
- Loading SPL with BOOT_DEVICE_RAM and breaking before SPL loads the
image to load U-Boot at the appropriate place. This can be a bit
tricky, because the load address is dependent on the header size. An
elf with symbols must also be used in order to stop at the appropriate
point. BOOT_DEVICE_SMH can be viewed as an extension of this process,
where SPL automatically stops and tells the host where to place the
image.
Signed-off-by: Sean Anderson <[email protected]>
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This does not use driver model and is more than two years past the
migration date. Drop it.
It can be added back later if needed.
Signed-off-by: Simon Glass <[email protected]>
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Drop the Kconfigs which are not used and all references to them. In
particular, this drops CONFIG_VIDEO to avoid confusion and allow us to
eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO.
Also drop the prototype for video_get_info_str() which is no-longer used.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Jason Liu <[email protected]>
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This converts the following to Kconfig:
CONFIG_PHY_RESET_DELAY
Cc: Ramon Fried <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2022.04-rc4
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The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.
Signed-off-by: Icenowy Zheng <[email protected]>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <[email protected]>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.
The only caveat is that this only works in the SPL, as the SPL header
gets overwritten with the exception vectors, once U-Boot proper takes
over. Always return MMC0 as the boot source, when called from U-Boot
proper, as a placeholder for now, until we find another way.
Signed-off-by: Jesse Taube <[email protected]>
Suggested-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <[email protected]>
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The switch_el macro is a neat contraption to handle cases where we need
different code depending on the current exception level, but its
implementation was longer than needed.
Simplify it by doing just one comparison, then using the different
condition codes to branch to the desired target. PState.CurrentEL just
holds two bits, and since we don't care about EL0, we can use >, =, < to
select EL3, EL2 and EL1, respectively.
Signed-off-by: Andre Przywara <[email protected]>
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asm/io.h is the header file containing the central MMIO accessor macros.
Judging by the header and the comments, it was apparently once copied
from the Linux kernel, but has deviated since then *heavily*. There is
absolutely no point in staying close to the original Linux code anymore,
so just remove the old cruft, by:
- removing pointless Linux history
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa)
This massively improves the readability of the file.
Signed-off-by: Andre Przywara <[email protected]>
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The ARMv8 architecture describes the "SError interrupt" as the fourth
kind of exception, next to synchronous exceptions, IRQs, and FIQs.
Those SErrors signal exceptional conditions from which the system might
not easily recover, and are normally generated by the interconnect as a
response to some bus error. A typical situation is access to a
non-existing memory address or device, but it might be deliberately
triggered by a device as well.
The SError interrupt replaces the Armv7 asynchronous abort.
Trusted Firmware enters U-Boot (BL33) typically with SErrors masked,
and we never enable them. However any SError condition still triggers
the SError interrupt, and this condition stays pending, it just won't be
handled. If now later on the Linux kernel unmasks the "A" bit in PState,
it will immediately take the exception, leading to a kernel crash.
This leaves many people scratching their head about the reason for
this, and leads to long debug sessions, possibly looking at the wrong
places (the kernel, but not U-Boot).
To avoid the situation, just unmask SErrors early in the ARMv8 boot
process, so that the U-Boot exception handlers reports them in a timely
manner. As SErrors are typically asynchronous, the register dump does
not need to point at the actual culprit, but it should happen very
shortly after the condition.
For those exceptions to be taken, we also need to route them to EL2,
if U-Boot is running in this exception level.
This removes the respective code snippet from the Freescale lowlevel
routine, as this is now handled in generic ARMv8 code.
Reported-by: Nishanth Menon <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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omap_ehci_hcd_stop appears to be dead code, and omap_ehci_hcd_init
is only called by the probe function, so it can be static to that
function. Remove both from the header along with some additional
checking for DM_USB.
Signed-off-by: Adam Ford <[email protected]>
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There are a few memory functions for both the emif4 (AM3517)
and sdrc (OMAP35/DM37) code that can be defined as static,
because those functions are not used externally. Make them
static and clean up some of the corresponding headers.
Signed-off-by: Adam Ford <[email protected]>
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With LTO enabled, some functions appear to be optimized in a
way that causes hanging on some OMAP3 boards after some
unrelated patches were applied. The solution appears to make
several functions __used. There also appears be to be some
dead code, so remove it while cleaning this up.
This has been tested on a general purpose OMAP3530, DM3730,
and AM3517.
Signed-off-by: Adam Ford <[email protected]>
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The interface for NOR/OneNAND is called "EIM" not "EMI". Fix this.
Signed-off-by: Harald Seiler <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Most Apple IOPs run a firmware that is based on what Apple calls
RTKit. RTKit implements a common mailbox protocol. This code
provides an implementation of the AP side of this protocol,
providing a function to initialize RTKit-based firmwares as well
as a function to do a clean shutdown of this firmware.
Signed-off-by: Mark Kettenis <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested on: Macbook Air M1
Tested-by: Simon Glass <[email protected]>
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U-Boot is expected to support multiple generations of Apple SoCs
in a single binary with a single defconfig. Therefore it makes
more sense to set SYS_SOC to "apple".
Signed-off-by: Mark Kettenis <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This converts the following to Kconfig:
CONFIG_SCSI_AHCI_PLAT
CONFIG_SYS_SCSI_MAX_SCSI_ID
CONFIG_SYS_SCSI_MAX_LUN
CONFIG_SYS_SATA_MAX_DEVICE
Drop CONFIG_SCSI for everything except the sandbox build. We only need
one build for tests.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This is defined based on two other CONFIGs for all boards except sandbox
and durian.
For sandbox the value does not matter. For durian the value seems
excessive.
Drop the option completely, to simplify configuration and reduce the
number of things we need to convert to Kconfig.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.
do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.
Signed-off-by: Keerthy <[email protected]>
[Amjad: fix IPU1_LOAD_ADDR and compile warnings]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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SION (Software Input On Field) - force the select mode input path
Signed-off-by: Angus Ainslie <[email protected]>
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Commit 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting")
made this macro unused. Then remove it.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
order to avoid AXI bus errors when GPU is enabled on the platform.
TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
derivatives, but is missing a lock settings to be applied.
Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
it implemented.
Since we're here, provide also names to bits from TRM instead of using
BIT() macro in the code.
Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors")
Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors")
Signed-off-by: Andrey Zhizhikin <[email protected]>
Cc: Peng Fan <[email protected]>
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Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.
On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into
an initramfs shell from ~6.1s down to ~1.2s.
Signed-off-by: Sven Schwermer <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.
And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.
A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The setting does not have effect because we should set it after
power on the PS16 for NIC AV.
So move it after upower_init which has powered on all PS
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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