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Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/
commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"
In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan <[email protected]>
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Add more fuse bank structure for use.
Signed-off-by: Peng Fan <[email protected]>
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imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.
Reviewed-by: Fugang Duan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.
Signed-off-by: Peng Fan <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.07
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- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
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Add REVC informaiton.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.
This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.
Signed-off-by: Patrick Delaunay <[email protected]>
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Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.
Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).
The patch also avoids to select simultaneously 2 configurations.
Signed-off-by: Patrick Delaunay <[email protected]>
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Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.
The module also adds some commands:
- snvs_cfg: Configure the SNVS HP and LP registers
- snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
- tamper_pin_cfg: Change the configuration of the tamper pins
- snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
status bits
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Franck LENORMAND <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Sync the latest SCFW API with below commit
6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add
interfaces for PM resource reset and read/write SNVS security
violation and tamper DGO registers.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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SECO provides APIs to support CAAM manufacturing protection:
- sc_seco_get_mp_key()
- sc_seco_get_mp_sign()
- sc_seco_update_mpmr()
Add SCFW APIs support.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The fracpll decoding is using the bit definitions for int pll. Most of
them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK
for fracpll and correct all bit definitions in fracpll decoding.
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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For ARM core clock, there are two input branches, and can select via mux:
one from ARM PLL directly, second from CCM A53 clock root.
Currently we are using second branch. But IC confirmed the CCM A53 root
signoff timing is 1Ghz, so we should switch to input from ARM PLL directly.
This patch fixes the CORE SEL slice configuration and switch ARM clock
to ARM PLL.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Update clock root table to let it be easy to configure clock at
very early stage. Also the core_sel mux parent should be A53 CLK
root and ARM PLL.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could
share same macro, then we no need to add is_imx6ulz in various drivers.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8MN variants support
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8MQ Dual and QuadLite variants.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type,
extend it to 0x1ff.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
platforms.
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This converts the following to Kconfig:
CONFIG_PHYLIB
CONFIG_BITBANGMII
CONFIG_MV88E6352_SWITCH
CONFIG_MV88E61XX_SWITCH
CONFIG_PHYLIB_10G
CONFIG_PHY_AQUANTIA
CONFIG_PHY_ATHEROS
CONFIG_PHY_BROADCOM
CONFIG_PHY_CORTINA
CONFIG_PHY_DAVICOM
CONFIG_PHY_ET1011C
CONFIG_PHY_LXT
CONFIG_PHY_MARVELL
CONFIG_PHY_MICREL
CONFIG_PHY_NATSEMI
CONFIG_PHY_REALTEK
CONFIG_RTL8211X_PHY_FORCE_MASTER
CONFIG_PHY_SMSC
CONFIG_PHY_TERANETICS
CONFIG_PHY_TI
CONFIG_PHY_VITESSE
CONFIG_PHY_XILINX
Signed-off-by: Tom Rini <[email protected]>
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Move GIC redistributor tables initialization to CPU setup function.
This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename the function so that it is more readable.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Wasim Khan <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Amit Singh Tomar <[email protected]>
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As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.
Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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- Backplane support and bug fixes
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
- Fix video output on GXBB/GXL/GXM boards
- add USB gadget support for GXL/GXM boards
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Add set_mode function in the Amlogic GXL PHYs that will be called by
the arch code to switch PHYs from/to gadget mode.
Signed-off-by: Neil Armstrong <[email protected]>
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This patch is to define esdhc_status_fixup function for ls1028a to disable
SDHC1/SDHC2 status in device tree node if not selected.
Signed-off-by: Yinbo Zhu <[email protected]>
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Yangbo Lu <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add support for i.MXRT by adding CONFIG_IMXRT in register structure and
adding .compatible = "fsl,imxrt-lcdif".
Signed-off-by: Giulio Benetti <[email protected]>
Reviewed-by: Anatolij Gustschin <[email protected]>
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The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Co-developed-by: Filip Brozović <[email protected]>
Signed-off-by: Bernhard Messerklinger <[email protected]>
Signed-off-by: Filip Brozovic <[email protected]>
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- Add support for Jetson Nano, plus miscellaneous other fixes found
during Nano bringup.
- Add Igor's update_uboot wrapper patches.
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According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.
These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,
RK3288:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_lvds: endpoint@2 {
reg = <2>;
remote-endpoint = <&lvds_in_vopb>;
};
vopb_out_mipi: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi_in_vopb>;
};
};
RK3399:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_mipi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
vopb_out_dp: endpoint@4 {
reg = <4>;
remote-endpoint = <&dp_in_vopb>;
};
};
here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.
The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.
Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.
Add the patch for fixing these vop modes for rk3399.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Tested-by: Peter Robinson <[email protected]>
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This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.
Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.
If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.
Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.
Signed-off-by: Masahiro Yamada <[email protected]>
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dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada <[email protected]>
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Make dma_map_single() return the dma address, and remove the
pointless volatile.
Signed-off-by: Masahiro Yamada <[email protected]>
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The Cortina CAxxxx GPIO driver maintains DM_GPIO support
across different CPU ISA in the CAxxxx Soc Family; Not just ARM.
Therefore, it is not desirable to split out and maintain separete
gpio header file for each CPU architecture.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jason Li <[email protected]>
Signed-off-by: Alex Nemirovsky <[email protected]>
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This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1012A
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Add cpu reset cause in common cpu-info file.
This would help to print the reset cause for
various resets.
Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a,
ls1088a platforms:
- lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes
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Subsystems such as USB expect dma_map_single() and dma_unmap_single() to
do dcache flush/invalidate operations as required. For example, see
see drivers/usb/gadget/udc/udc-core.c::usb_gadget_map_request().
Currently drivers do this locally, (see drivers/usb/dwc3/ep0.c,
drivers/mtd/nand/raw/denali.c etc..)
Update arch specific dma_map_single() and dma_unmap_single() APIs to do
cache flush/invalidate operations, so that drivers need not implement
them locally.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Add an arch-specific handoff header so that we can use the HANDOFF feature
on arm devices.
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Exports the serdes configuration as an environment variable for LS gen 3
SoCs, so it can be used in u-boot command line. It should particularly
be useful for applying Linux DT overlays for the given serdes
configuration.
This code is called from arch_misc_init and not from the existing
serdes_init function because it depends on U-Boot environment being set
up.
Signed-off-by: Alex Marginean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcm68360.
Signed-off-by: Philippe Reynes <[email protected]>
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