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mmu_status is used in io memcpy functions to prevent accesses to non
8-byte aligned addresses when the mmu is disabled. Though there is a
redundant definition enabled when icaches is turned off by setting
SYS_ICACHE_OFF.
This patch removes the redundant definition, allowing mmu_status to
properly report the status regardless of config settings. This shouldn't
be a problem since access to non 8-byte aligned data can be done
irrespective of icache state.
Fixes: 268f6ac1f95c ("arm64: Update memcpy_{from, to}io() helpers")
Signed-off-by: Anshul Dalal <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* DDR updates:
- IOSSM mailbox compatibility check
- Correct DDR calibration status handling
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
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For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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USB 3.1 node is enabled for Agilex5.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.
Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).
Without this check, builds with dcache disabled will fail to compile.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.
Signed-off-by: Mahesh Rao <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.
Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.
This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Change is to allow the user to choose speed and mode values
from dts or the default ones.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add NAND node to the base stratix10 dtsi file.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In order to circumvent CCU NOC issue in Agilex5, it is recommended
to disable cache allocation for reads. This prevents hang issues
caused by CCP (Common Cache Pipe) Fill Done FIFO overflow.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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This series from Debbie Horsfall <[email protected]> enhances the
Vexpress64 platform in a few ways.
Link: https://lore.kernel.org/r/[email protected]
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Select SYSRESET on Vexpress64 to enable system reset to support other
features, such as capsule-on-disk. Select SYSRESET_PSCI if PSCI is
inferred from the firmware (via ARM_PSCI_FW).
Select ARM_SMCCC for Vexpress64 boards which in turn selects
ARM_PSCI_FW.
The sysreset uclass unconditionally implements a reset_cpu() function.
Remove the empty reset_cpu() in vexpress64 board code.
Signed-off-by: Debbie Horsfall <[email protected]>
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U-Boot now stashes its bootstage buffer into a reserved memory region
whenever CONFIG_BOOTSTAGE_STASH is enabled, just before exiting to the
kernel. This allows a post boot parser to read a unified timeline
(SPL→U-Boot→Kernel→MCU/DSP) directly from DDR, enabling standardized
and repeatable boot-time profiling across releases and SoCs.
Change summary:
Call bootstage_stash_default() in announce_and_cleanup()
when CONFIG_BOOTSTAGE_STASH is set.
Reference boot-time parser utility:
https://github.com/v-singh1/boot-time-parser
Sample boot time report:
+--------------------------------------------------------------------+
am62xx-evm Boot Time Report
+--------------------------------------------------------------------+
Device Power On : 0 ms
SPL Time : 843 ms
U-Boot Time : 2173 ms
Kernel handoff time : 462 ms
Kernel Time : 2522 ms
Total Boot Time : 6000 ms
+--------------------------------------------------------------------+
+--------------------------------------------------------------------+
Bootloader and Kernel Boot Records
+--------------------------------------------------------------------+
BOOTSTAGE_AWAKE = 0 ms (+ 0 ms)
BOOTSTAGE_START_UBOOT_F = 843 ms (+ 0 ms)
BOOTSTAGE_ACCUM_DM_F = 843 ms (+ 0 ms)
BOOTSTAGE_START_UBOOT_R = 1951 ms (+1108 ms)
BOOTSTAGE_ACCUM_DM_R = 1951 ms (+ 0 ms)
BOOTSTAGE_NET_ETH_START = 2032 ms (+ 81 ms)
BOOTSTAGE_NET_ETH_INIT = 2053 ms (+ 21 ms)
BOOTSTAGE_MAIN_LOOP = 2055 ms (+ 2 ms)
BOOTSTAGE_START_MCU = 2661 ms (+606 ms)
BOOTSTAGE_BOOTM_START = 2959 ms (+298 ms)
BOOTSTAGE_RUN_OS = 3016 ms (+ 57 ms)
BOOTSTAGE_BOOTM_HANDOFF = 3016 ms (+ 0 ms)
BOOTSTAGE_KERNEL_START = 3478 ms (+462 ms)
BOOTSTAGE_KERNEL_END = 6000 ms (+2522 ms)
+--------------------------------------------------------------------+
+--------------------------------------------------------------------+
MCU Boot Records
+--------------------------------------------------------------------+
MCU_AWAKE = 2661 ms (+ 0 ms)
BOARD_PERIPHERALS_INIT = 2661 ms (+ 0 ms)
MAIN_TASK_CREATE = 2661 ms (+ 0 ms)
FIRST_TASK = 2662 ms (+ 1 ms)
DRIVERS_OPEN = 2662 ms (+ 0 ms)
BOARD_DRIVERS_OPEN = 2662 ms (+ 0 ms)
IPC_SYNC_FOR_LINUX = 6636 ms (+3974 ms)
IPC_REGISTER_CLIENT = 6636 ms (+ 0 ms)
IPC_SUSPEND_TASK = 6636 ms (+ 0 ms)
IPC_RECEIVE_TASK = 6636 ms (+ 0 ms)
IPC_SYNC_ALL = 6787 ms (+151 ms)
+--------------------------------------------------------------------+
Signed-off-by: Vishnu Singh <[email protected]>
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Add MIDR entry for Cortex-A720 core.
Signed-off-by: Marek Vasut <[email protected]>
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The most of OFFSET values are in hex instead of int which is easier for
layout description.
Signed-off-by: Michal Simek <[email protected]>
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Add PCIE1 and PCIE2 ECAM space and outbound space to MMU pagetable,
so A55 can access them.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add board-level code and defconfig for the i.MX943 EVK board, supporting
multiple SOM variants: 19x19 LPDDR5, 19x19 LPDDR4 and 15x15 LPDDR4.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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Introduce the base dtsi files for the i.MX943 EVK board. These files
define the essential components such as messaging units, uSDHC, GPIOs
and lpuart for board bring-up.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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Extend display_life_cycle() to support i.MX94.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
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The register reflects lifecycle and some lifecycle-derived state of
i.MX95 has new offset address and layout, so display_life_cycle() is
added specifically for it.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Due to i.MX95 has reserved first 256MB DDR, change to use the DDR
start address in u-boot as the container header buffer.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Extend get_imageset_end() to handle i.MX94 family.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
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i.MX94
- Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94.
- Introduce common.h with macros of clock IDs, power domains, and CPU
types for platform-specific replacement (e.g., i.MX94, i.MX95).
- Extend imx_get_mac_from_fuse() to support i.MX94.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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Update get_reset_reason() to support i.MX94 to send message to the
System Manager to retrieve the LM/system last booted/shutdown reasons.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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reasons
System Manager provides the last booted and shutdown reasons of the
logical machines (LM) and system using the SCMI misc protocol (Protocol
ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query
and print these reasons in SPL and U-Boot.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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Introduce support for the new i.MX94 processor, including its CPU type
and SoC-level Kconfig entry.
The i.MX94 is a new member of the i.MX9 family. It uses a System Manager
to handle system-level functions such as power, clock, sensor and pin
control. The System Manager runs on a Cortex-M processor, while the
Cortex-A processor communicates with it via the ARM SCMI protocol and a
messaging unit.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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On the RZG2L platform, the advised
TF-A (https://github.com/renesas-rz/rzg_trusted-firmware-a/tree/v2.5/rzg2l)
does not pass any DTB blob to U-Boot.
On the other hand, the RZG2L part of U-Boot expects a DTB to be passed. It
means that if one flashes the latest TF-A as well as the mainline U-Boot,
it will crash trying to dereference the NULL DTB pointer before outputing
anything.
Check if the DTB pointer is NULL before trying to use it.
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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and fix related test/DTS issues""
This reverts commit 4d84fa1261eb27d57687f2e4c404a78b8653c183, reversing
changes made to b82a1fa7ddc7f3be2f3b75898d5dc44c34420bdd.
I had missed some feedback on this series from earlier, and we have
since had reports of regressions due to this as well. For now, revert
this.
Signed-off-by: Tom Rini <[email protected]>
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related test/DTS issues"
Aristo Chen <[email protected]> says:
This patch series enhances FIT image robustness by adding **memory
region overlap detection** to `mkimage` and fixing existing overlaps
in DTS files and `binman` tests.
The primary goal is to prevent runtime memory corruption from
conflicting load addresses in FIT images.
Key Changes:
1. `mkimage` Overlap Detection: A new validation in
`tools/fit_image.c` checks for overlapping load addresses
within FIT configurations. `mkimage` now errors out with
detailed info on conflicts, preventing bad FIT image creation.
2. New Test Case: A Python test verifies the new detection.
It intentionally creates an overlap (kernel and FDT)
to confirm correct error handling.
3. Fixes for Existing Overlaps:
* Board DTS (k3-am6xx): Adjusted load addresses for TI
firmware stubs to prevent conflicts. This resolves
previously undetected overlaps.
* `binman` Tests: Fixed several tests. U-Boot load
addresses were shifted to avoid ATF conflicts. A new
linker script for TEE ELF sections ensures distinct
memory layouts.
4. Documentation: Added guidance for developers on how to
determine ELF load addresses using readelf, linker scripts,
and objdump when working with binman FIT images.
Impact:
This series improves FIT image reliability by catching overlaps
at build time, helping developers resolve issues before runtime
failures.
Link: https://lore.kernel.org/r/[email protected]
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Fix memory overlaps in FIT image configurations for TI AM62x and AM64x
PHYCore and SK boards.
The overlaps occurred in two categories:
1. TI firmware stub images (tifsstub-hs, tifsstub-fs, tifsstub-gp):
These mutually exclusive firmware variants were incorrectly assigned
the same load address within FIT configurations, causing overlap
detection to fail. Adjust addresses with 64KB spacing:
- tifsstub-hs: Keep original address
- tifsstub-fs: Move to +64KB offset
- tifsstub-gp: Move to +128KB offset
2. Device tree overlay images (som-no-rtc, som-no-spi, som-no-eth):
These overlay files had insufficient spacing between load addresses,
causing actual memory overlaps. Increase spacing to 8KB boundaries
to accommodate overlay sizes safely.
An upcoming commit will validate if the memory region is overlapped
Signed-off-by: Aristo Chen <[email protected]>
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Prepare v2025.10-rc5
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The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong
value is used in ccm_reg structure and Coverity reports several
issues as out-of-bounds write.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The ELE MU driver needs to be probed at init_r phase as well because
some ELE APIs will be called.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Use fixed seq 0 and 1 for enetc PCI buses, then the seq for PCI controllers
could start after them.
Signed-off-by: Ye Li <[email protected]>
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We have to explicitly assign HSIOPLL_VCO as HSIOPLL parent. So when
enabling HSIOPLL, its parent HSIOPLL_VCO will be enabled firstly.
Signed-off-by: Ye Li <[email protected]>
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The ahab_commit command allows the user to commit into the SECO fuses
that control the SRK key revocation information. This is used to Revoke
compromised SRK keys.
To use ahab_commit, the boot container must be built with an SRK
revocation bit mask that is not 0x0. For the SPSDK provided by NXP, this
means setting the 'srk_revoke_mask' option in the config file used to
sign the boot container. The 'ahab_commit 0x10' can then be used to commit
the SRK revocation information into the SECO fuses.
Signed-off-by: John Ripple <[email protected]>
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The config "GIC_V3" seems to be typo, and currently "GICV3" remains
disabled. This should be removed until needed.
Fixes: 5cd4a355e0f0 ("board: synquacer: Add DeveloperBox 96boards EE support")
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Add flash0 partitions for stm32mp257f-ev1-u-boot.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace RIFSC check access APIs by grant/release access ones that handle
the RIF semaphores.
Signed-off-by: Gatien Chevallier <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Fix RIFSC semaphores acquisition by not returning an error when the
current CID already possess the semaphore. Also fix an incorrect mask
for the CID value in the SEMCR register.
Signed-off-by: Gatien Chevallier <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27660
- Restore the support for the i.MX95 A0 silicon.
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Enable HBMC in the R5 SPL stage
Fixes: c9df79ee64d0 ("arm: dts: k3-j721e-r5-common: Add HBMC overrides for R5 SPL")
Signed-off-by: Anurag Dutta <[email protected]>
Reviewed-by: Udit Kumar <[email protected]>
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This patch is used to restore support for i.MX95 A0 silicon. To avoid
duplicating defconfig, imx95.config is added and can be shared between
imx95_a0_19x19_evk_defconfig and imx95_19x19_evk_defconfig.
container.cfg and imximage.cfg are used to created .cfgout files that
are be passed to mkimage with -n to build flash.bin. Now they have been
deleted and replaced by adding their content to properties of node which
type is nxp-imx9image under binman node.
Fixes: 9936724aa9b ("imx95_evk: Add i.MX95 B0 support")
Signed-off-by: Alice Guo <[email protected]>
Tested-By: Tim Harvey <[email protected]> # imx95-19x19-evk (rA0)
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fdtdec_get_addr_size uses architecture dependent datatypes which causes
the 32-bit R5 to fail when reading the 64-bit size and addr fields of
reg nodes from the fdt.
Therefore change it to a common api for both 64 and 32 bit platforms to
allow for fdt fixups from R5.
Fixes: 8b0fc29de0e3 ("arm: mach-k3: am62: Fixup TF-A/OP-TEE reserved-memory node in FDT")
Signed-off-by: Anshul Dalal <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
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SPL recover data section is broken which causes reboot failure on
some i.MX platforms (iMX8QM/iMX95).
The global variable cold_reboot_flag is assigned to weak reset_flag
function which always return 1, so restore never been executed in
warm reboot.
Fixes: 1c37e59bfbba ("arm: armv8: Improve SPL data save and restore implementation")
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Steffen Kothe <[email protected]> says:
AM64X hereby receives support for reset reason printing during boot.
Unfortunately does the AM64X register mapping slighlty differ from
the AM62X. WDT and PORZ are not part of the reset source register, but
the mapping remains the same for all other causes.
To prevent ifdef/else constructs, I decided to follow a simple
copy/paste approach and adjusted the logic accordingly.
Link: https://lore.kernel.org/r/[email protected]
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Implement get_reset_reason() for AM64x to enable reporting of the reset
cause in the cpuinfo output.
Notice that the AM64x does not support dedicated reset cause bits for
WDT and PORZ as the AM62x does.
An explanation of this difference is not part of the technical reference
manual and remains unclear.
Signed-off-by: Steffen Kothe <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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AM64X SoCs use similar but not identical bit mappings like the AM62X
family.
In detail does the AM64X not support PORZ and WDT as reset caused.
Add the mapping according to the technical reference manual into the
SoC specific header.
Signed-off-by: Steffen Kothe <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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