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R-Car V4H Sparrow Hawk EVTB1
This partly reverts commit 1df2880e9512f4760f615668e5d06aa5f44b778a.
This change is part of Linux 6.18.y DTs as commit
7d1e3aa2826a ("arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1")
Drop the duplicate change from U-Boot DT.
Signed-off-by: Marek Vasut <[email protected]>
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Retronix R-Car V4H Sparrow Hawk EVTB1
This reverts commit 74bc80190c48dce43a59cbae1975ccf10f671bc2.
This change is part of Linux 6.18.y DTs as commit
ae95807b00e1 ("arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1")
Drop the duplicate change from U-Boot DT.
Signed-off-by: Marek Vasut <[email protected]>
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R-Car V4H Sparrow Hawk board
This reverts commit 797255d897d635799fbb878262b7491e07ceac9e.
This change is part of Linux 6.18.y DTs as commit
95319aaa3ffc ("arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support")
Drop the duplicate change from U-Boot DT.
Signed-off-by: Marek Vasut <[email protected]>
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Move the SCP initialization from board file into remoteproc driver
where this is supposed to be. Add SCP MDLC DT node and describe the
SCP reset controlled by the SCP MDLC in remoteproc DT node. Adjust
the driver to control the SCP reset via reset framework instead of
the current board-specific register poking.
Signed-off-by: Marek Vasut <[email protected]>
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With commit 607d45d1e3b3 ("power: pmic: tps65219: fail if regulators
node is missing"), the driver requires the PMIC node to have regulator
nodes.
Since we don't have bootph tags in the regulator child nodes, the
resulting DTB doesn't have any regulator child nodes for the SPL phase
leading to boot failures. Therefore this patch explicitly adds the
bootph-all tag to all regulator nodes for the beagleplay.
Signed-off-by: Anshul Dalal <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip/-/pipelines/972
- Disable JTAG for RK3576. Fix for boards potentially not being able to
use SD card anymore due to automatic switch to JTAG based on level of
one specific pin,
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The M-PHY and SRAM readiness poll loops move out of the UFS controller
driver and into the firmware backend, exposed as blocking waits with
a caller-owned timeout budget. This keeps the UFS driver backend-agnostic
and lets an other backends offload the wait to the platform in a single
call instead of round-tripping every poll.
set_sram_bypass() now performs the SRAM_CSR read-modify-write in the
firmware layer.
Hook up functions are also update to reflect their usage.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/26bc9aa2c02921690e126ab3401f7974ef04ad6e.1785394153.git.michal.simek@amd.com
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Add firmware interface for UFS access but also keep IO interface when
firmware is not enabled.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/6419fe4f6f1f451aee624c7762b7aa690d50e498.1784870711.git.michal.simek@amd.com
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The GIC redistributor base address depends on the part: the 2VM3654
device has 4 APU cores and 3 GIC ITS blocks, which shifts the
redistributor region up compared to the base 8 core / single ITS part.
A single U-Boot binary must therefore pick the right base at runtime
instead of relying on the compile-time GICR_BASE used by the generic
lowlevel_init().
Add a SoC specific lowlevel_init() that reads the PMC TAP IDCODE and
selects GICR_BASE_2VM3654 for the 2VM3654 device, otherwise keeps the
default GICR_BASE. CONFIG_ARMV8_MULTIENTRY is not supported on Versal
Gen 2 so the generic slave handling is intentionally dropped.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/4c0dc2b6e29d300db15be0844879ab4d028d98a9.1783493630.git.michal.simek@amd.com
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The register address and bootmode defines in this header are useful from
early assembly (e.g. lowlevel_init reading PMC_TAP_IDCODE), but the file
could not be included from .S because the C-only declarations were not
guarded.
Reorder the header so all plain address/value defines are visible to both
C and assembly, and move every C-only construct (the linux/bitops.h
include, the register structs, the base pointer-cast macros and the
platform enum) into a single #ifndef __ASSEMBLY__ block.
No functional change for C consumers.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/de4de47ea457b285c5870e7ba25b4baf554561e7.1783493630.git.michal.simek@amd.com
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Rockchip SoCs can automatically switch between jtag and sdmmc based on
the following rules:
- all the SDMMC pins including SDMMC_DET set as SDMMC function in GRF,
- force_jtag bit in GRF is 1,
- SDMMC_DET is low (no card detected),
Note that the BootROM may mux all SDMMC pins in their SDMMC function or
not, depending on the boot medium that were tried.
Because SDMMC_DET pin is not guaranteed to be used as an SD card card
detect pin, it could be low at boot or even switch at runtime, which
would enable the jtag function and render the SD card unusable.
Or boards using cd-gpios may switch the SDMMC_DET pin to GPIO function,
which would enable the jtag function and render the SD card unusable.
With commit d0a838bdc629 ("Subtree merge tag 'v7.1-dts' of dts repo [1]
into dts/upstream") there are now RK3576 boards that have changed to use
cd-gpios for the SDMMC_DET pin, e.g. NanoPi R76S, that may have issues
detecting SD card unless force_jtag is disabled.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
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The TF-A DRAM bank setup currently assumes that the number of
banks reported by TF-A matches the number of entries available in
gd->bd->bi_dram[]. Limit the loop by CONFIG_NR_DRAM_BANKS so that
a platform with fewer configured DRAM banks does not write past the
array.
The reserved RAM setup also checks higher DRAM banks before falling
back to bank 0. When a higher bank is empty and board_reserve_ram_top()
returns 0, the old test succeeds for a zero-sized bank. This can set
gd->arch.resv_ram to 0.
On systems with CONFIG_GIC_V3_ITS this value is later used by
ls_gic_rd_tables_init() to place the GIC LPI tables:
gd->arch.resv_ram - GIC_LPI_SIZE
If gd->arch.resv_ram is 0, the subtraction underflows and the GIC LPI
tables are placed at an invalid high address.
Skip empty banks when selecting the reserved RAM area and fail GIC LPI
table setup if no reserved RAM address was established.
This fixes LS1028A systems with 2 GiB of RAM, where TF-A reports only
one populated DRAM bank.
Tested on an LS1028ARDB with TF-A modified to report 2 GiB of RAM, and
on a custom LS1028A-based board equipped with 2 GiB of RAM.
Signed-off-by: Patryk Biel <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Fix many dtc warning for the Layerscape device trees with W=1.
Without this fix, it emits over 30 unit_address_format warnings.
No functional change.
Signed-off-by: Vincent Jardin <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Enable main_uart2 and main_uart3 for console log functionality.
Add clk and device data for main_uart2 and main_uart3
which can be used by main_uart driver to configure clocks and PSC.
Signed-off-by: Gokul <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-usb
- MTU3 DT bindings alignment with Linux DT bindings.
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The MTU3 glue driver expects a synthetic mediatek,ssusb child that
combines the device and xHCI register windows. Upstream devicetrees
instead put the device resources on the controller node and describe the
xHCI window with a standard child node, so U-Boot cannot use an upstream
topology.
Switch to the upstream layout. The controller owns the shared resources
and the device MAC, with the device register offsets relative to it as in
Linux. The gadget role binds as a node-less internal device, while the
host role binds to an enabled xHCI child and uses its own clocks,
supplies and register window. dr_mode selects the role and defaults to
otg, and the Kconfig choice constrains which role the build provides.
The legacy child layout is rejected explicitly so its combined register
window cannot be mistaken for the device MAC.
Convert the in-tree MT8183 and MT8512 devicetrees in the same commit so
neither platform is left without USB. MT8512 stays peripheral-only
because its xHCI host interrupt is not documented and the
mediatek,mtk-xhci binding requires it.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-sh
This includes temporary U-Boot DT ECC carveouts for R-Car Gen5, they
will be dropped from U-Boot DTs once OF_UPSTREAM DTs get re-synced.
This also includes RPC-IF support for R-Car Gen5 and env storage in RPC
HF.
This also includes an update for R-Car Gen5 UFS controller driver.
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The DBSC5 DRAM controller protects DRAM content using inline ECC.
The inline ECC utilizes areas of DRAM for its operation, which are
in the DRAM address range, but must not be accessed or modified.
Describe the inline ECC carveout areas used by the DBSC5 controller
on this hardware as reserved-memory, which must not be accessed.
Include DRAM areas which are unprotected by ECC as well, those are
parts of the DRAM which directly precede the ECC carveout.
In case of high DRAM utilization, unless the inline ECC carveouts
are properly reserved, Linux may use and corrupt the memory used
by the DBSC5 DRAM controller for inline ECC, which would lead to
the system becoming unstable.
Ported from Linux 7.2-rc5 commit
6fa6ee724d8d ("arm64: dts: renesas: ironhide: Describe inline ECC carveouts")
Signed-off-by: Marek Vasut <[email protected]>
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Fully describe all available DRAM in the DT, and describe regions which
are not accessible because they are used by firmware in reserved-memory
nodes.
Replace the first memory bank memory@60600000 with memory@40000000 and a
518 MiB long reserved-memory no-map subnode. This memory region is used
by other cores in the system.
Reserve 32 kiB of memory at 0x8c100000 for parameters shared by IPL,
SCP, TFA BL31 and TEE.
Reserve 512 kiB of memory at 0x8c200000 for TFA BL31. The upcoming
upstream TFA 2.15 BL31 uses memory from 0x8c200000..0x8c242fff; rounding
up to 512 kiB is slight future-proofing.
Reserve 32 MiB of memory at 0x8c400000 for OPTEE-OS, which is the entire
OPTEE-OS TZ protected DRAM area.
Neither TFA BL31 nor OPTEE-OS modify the DT passed to Linux in any way
with any new reserved-memory {} nodes to reserve memory areas used by
the TFA BL31 or OPTEE-OS to prevent the next stage from using those
areas, which lets Linux use all of the available DRAM as it is described
in the DT that was passed in by U-Boot, including the areas that are
newly utilized by TFA BL31 or OPTEE-OS.
In case of high DRAM utilization, unless the memory used by TFA BL31 or
OPTEE-OS is properly reserved, Linux may use and corrupt the memory used
by TFA BL31 or OPTEE-OS, which would lead to the system becoming
unresponsive.
Ported from Linux 7.2-rc5 commit
5250b3b1ad99 ("arm64: dts: renesas: ironhide: Describe all reserved memory")
Signed-off-by: Marek Vasut <[email protected]>
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Bind RPC and HyperFlash in DT on R-Car R8A78000 X5H Cortex-M33 RSIP.
RPC is used both to update the HF content, which includes the U-Boot on
RSIP itself and SCP firmware, as well as access the U-Boot environment
for U-Boot on RSIP.
Signed-off-by: Marek Vasut <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-imx
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-imx/-/pipelines/906
- Fix a boot regression on i.MX7 related to the system counter.
- Add Aquila iMX95 0243 PID4.
- Update phycore_imx8mm DDR timings.
- Add FRDM-IMX95 initial support.
- Handle FCFB header during SPI NOR boot and CST backend selection.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek
* Clock fix for MT8188 (Genio 700/520)
* SPL support preparatory patch for MT8188.
* Compile error fix for when enabling LWIP network stack on some MediaTek targets.
* Fix a regression in clock driver binding from the previous PR.
* Add display-related clocks on MT8188.
* Another wave of clock driver refactoring and de-duplication.
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Add boot support and peripherals like eMMC/SD, UART, I2C, GPIO, ENETC0/1
and PCIE0/1 for iMX95 15x15 FRDM.
Updated doc for build instructions.
Signed-off-by: Lei Xu <[email protected]>
Signed-off-by: Joseph Guo <[email protected]>
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MT8188 reset_cpu() checks the U-Boot proper PSCI symbol even when the
function is built for SPL. A standalone SPL download agent runs before
BL31, so fastboot acknowledges a reboot request and then stalls while
attempting an unavailable PSCI system reset.
Use the phase-aware configuration check so SPL falls back to the
watchdog reset provider. U-Boot proper continues to use PSCI as before.
Signed-off-by: Carlo Caione <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260724-ccaione-upstream-mt8188-spl-reset-v1-1-08da6554ecd8@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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imx_gpcv2_init() calls udelay(), which through schedule() reaches
cyclic_run(). Since commit 9c1b13b3fd27 ("cyclic: reduce get_timer_us()
calls inside hlist_for_each_entry_safe()") get_timer_us() is called even
when no cyclic function is registered, so tick_to_time_us() divides by a
still zero CNTFRQ and __div0() hangs the board before the console is up.
The requested delay was a no-op as well, since us_to_tick() reads a CNTFRQ
of zero.
Initialize the system counter before imx_gpcv2_init(), and move the
"already initialized" guard from timer_get_boot_us() into timer_init() so
that the later timer_init() from the generic init sequence is a no-op.
Where the system counter timer_init() is not compiled in, the weak
definition is empty and the calling it is harmless.
Fixes: b059837850e4 ("imx: mx7: add gpc initialization for low power mode")
Fixes: 9c1b13b3fd27 ("cyclic: reduce get_timer_us() calls inside hlist_for_each_entry_safe()")
Signed-off-by: Emanuele Ghidoli <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Only print origin and errid fields when the corresponding valid bits
(MISC_BOOT_FLAG_ORG_VLD and MISC_BOOT_FLAG_ERR_VLD) are set. For a
normal power-on reset, these fields are not valid, and printing -1
is just noise.
Signed-off-by: Joseph Guo <[email protected]>
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The Phytec Tauri L is sold with multiple memory configurations beyond the
base 2 GB variant. To support these alternative capacities seamlessly,
read the physical memory size directly from the EEPROM of the underlying
phyCORE module and apply the appropriate DDR timing parameters at runtime.
Alternatively, a fixed memory configuration can still be enforced via a
dedicated Kconfig option if dynamic detection is not desired.
Note that while U-Boot correctly discovers the full physical memory bank,
the device tree excludes the memory beyond 3 GB (below the 4 GB boundary).
This ensures that U-Boot allocations and early EFI staging buffers remain
safe from 32-bit interconnect DMA limitations inherent to some i.MX8MM
IP blocks.
Signed-off-by: INgo Rah <[email protected]>
Reviewed-by: Gregor Herburger <[email protected]>
Reviewed-by: Benedikt Spranger <[email protected]>
Reviewed-by: Yannic Moog <[email protected]>
Tested-by: Yannic Moog <[email protected]>
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Remove OPP DT nodes from R-Car H3, M3-W, M3-W+ and M3-N DTs,
those nodes are not used by U-Boot and only increase the control
DT size and complexity. This saves about 1 kiB on the resulting
U-Boot binary without any impact on functionality.
Signed-off-by: Marek Vasut <[email protected]>
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description for Sparrow Hawk"
This reverts commit a6f018b7b503c026cc66d25bd59868bac70150dc.
The a6f018b7b503 ("arm64: dts: renesas: r8a779g3: Reinstate basic PCIe
clock description for Sparrow Hawk") workaround for missing PCIe clock
generator driver is no longer necessary, as the Renesas 9-series PCIe
clock generator driver is now available. Drop the workaround.
Signed-off-by: Marek Vasut <[email protected]>
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The x960-28YSQ is a 25G/100G layer 3 switch from Allied Telesis.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
[sr: fix DT file name in MAINTAINERS]
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Add IDs for more of the Alleycat3 and Poncat3 variants. This makes the
SoC information at boot say something other than "Unknown-??".
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Once we move to the v7.0-dts tag, we get a failure to build of:
dts/upstream/src/arm64/qcom/ipq5424.dtsi:556.21-573.5: ERROR (phandle_references): /soc@0/mmc@7804000: Reference to non-existent node or label "sdc_default_state"
also defined at arch/arm/dts/ipq5424-rdp466-u-boot.dtsi:20.8-39.4
ERROR: Input tree has errors, aborting (use -f to force output)
Looking over the changes, this appears to be what's required to keep the
platform functioning as expected.
Acked-by: Casey Connolly <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When moving to the v7,1-dts tag, we see a few problems trying to build
this platform. In turn, when looking at the upstream changes we can see
that USB3 support has been included now, but isn't exactly the same as
in our tree either. Modify things such that we build again.
Signed-off-by: Tom Rini <[email protected]>
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Add mcu_i2c0 to access the pmic watchdog control registers.
Signed-off-by: Dominik Haller <[email protected]>
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The eMMC and SD card on the sc598 share pins, so they cannot be
used at the same time. Previously, this was managed with a patch applied
by the relevant build system, but patches are brittle and have to be
maintained. Instead, they have been replaced with two separate device trees
, one for eMMC and one for SD card, which inherit a shared base dtsi.
The build system can then select between the default device tree which
enabled eMMC or the other device tree which enables SD card support.
Signed-off-by: Caleb Ethridge <[email protected]>
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Chintan Vankar <[email protected]> says:
This series enables Ethernet boot on SK-AM62A-LP. The series is based on
commit 'a18265f1ccb7' of origin/next branch of U-Boot repo.
Link: https://lore.kernel.org/r/[email protected]
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Enable DM services for main_pktdma during R5 SPL stage.
Tested-by: Anshul Dalal <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-imx
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-imx/-/pipelines/749
- Support authenticating signed Mcore container image on i.MX9.
- Support booting CM70, CM71 and CM33 sync cores on i.MX9.
- Add i.MX SNVS RTC driver.
- Detect RAM sizes on Toradex smarc and aquila i.MX95 boards.
- Add support for the Librem5 devkit.
- Subtract half a cycle instead of three quarters of a cycle after DQS
gating calibration on i.MX6.
- Several tqma6 improvements.
- Add product ID support for new Toradex boards.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-sunxi
Beside a fix for a long standing bug in the A80 eMMC code, this adds
SPI booting support for the Allwinner A523/A527/T527 class of boards.
The second major feature is support for the secondary Ethernet controller
on that same SoC. This might not be as important as for the kernel (I
doubt that U-Boot acts as a router), but for once some boards only connect
the secondary EMAC, and on others people might have the boot server only
reachable via this port.
There are some smaller fixes and improvements still queued up, but they
need some more testing and are minor, so can land a bit later.
The world build timed out, but the rest passed, and I booted that briefly
on an A523 board with two Ethernet ports.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip
- Switched to use upstream pinctrl header include,
- Dropped SDHCI DT properties in U-Boot-specific DT for NanoPi R5 as
most are present upstream and those which aren't are breaking devices,
- Fixed ECC strength mismatch between reading and writing on non-0
NAND chips configured as boot medium (nand-is-boot-medium),
- Moved Simon to reviewer for ARM ROCKCHIP,
- Fixed build issue related to GPT capsule support accessing a struct
member only present when CONFIG_PARTITION_TYPE_GUID is set,
- Added support for new devices:
- Anbernic RG-DS
- ROC-RK3588S-PC
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No longer required due to the use of upstream device trees.
Signed-off-by: Max Merchel <[email protected]>
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Add boot phase properties from U-Boot device tree.
This commit can be reverted if changes are integrated in upstreem
device trees and synced with U-Boot.
Signed-off-by: Max Merchel <[email protected]>
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We will need GPIO to distinguish between SOM variants with / without
workaround for ENET errata. This is necessary to implement the
appropriate solution and remove code intended for the non-DM use case.
To support reuse, split them in SOM and baseboard specific parts.
Prepare fragments for use with SPL.
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Max Merchel <[email protected]>
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Since iMX952 only has 2 pf and 2 vf, update the imx_get_mac_from_fuse
to adapt this layout.
Signed-off-by: Ye Li <[email protected]>
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Add missing firmware/optee node, so is can be both used and copied into
Linux device tree by optee_copy_firmware_node(). This is consistent with
other i.MX93 boards.
Signed-off-by: Mathieu Dubois-Briand <[email protected]>
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The FSPI header is now generated purely using binman, drop no longer
supported nxp,fspi-header-filename property.
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The FSPI header is now generated purely using binman, drop no longer
supported nxp,fspi-header-filename property.
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Select TQ_COMMON_SYSINFO to use the tq_eeprom sysinfo driver
to read and print module EEPROM data.
Signed-off-by: Max Merchel <[email protected]>
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Add sysinfo node for tq,eeprom sysinfo driver.
Signed-off-by: Max Merchel <[email protected]>
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TQMa6UL has board-information located in EEPROM at offset 0x20.
Add necessary nodes and properties for nvmem-cells.
Revert this commit once the upstream linux device trees are
accepted and synchronized.
Signed-off-by: Max Merchel <[email protected]>
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