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This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present
Signed-off-by: Simon Glass <[email protected]>
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Mostly including the Armada 37xx pinctrl / gpio driver.
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Currently these (board agnostic) commands cannot be selected using
menuconfig and friends. Fix this the obvious way. As part of this,
don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v'
and "we have a hashing command" as this makes the Kconfig logic odd.
Signed-off-by: Daniel Thompson <[email protected]>
[trini: Re-apply, add imply for a few cases, run moveconfig.py, also
migrate CRC32_VERIFY]
Signed-off-by: Tom Rini <[email protected]>
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The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Nathan Rossi <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting
the correct PHY type (KR / SFI) for the COMPHY driver and enabling the
ethernet0 device node in the dts.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefan Chulski <[email protected]>
Cc: Kostya Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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Start to populate the device tree of the Armada 37xx with the pincontrol
configuration used on the board providing a dts.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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Add the nodes for the two pin controller present in the Armada 37xx SoCs.
Initially the node was named gpio1 using the same name that for the
register range in the datasheet. However renaming it pinctr_nb (nb for
North Bridge) makes more sens.
Minor changes for U-Boot because of the slightly different dts version
done by Stefan Roese.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below
Image Flash Offset
RCW+PBI 0x00000000
Boot firmware (U-Boot) 0x00100000
Boot firmware Environment 0x00300000
PPA firmware 0x00400000
PHY firmware 0x00980000
DPAA2 MC 0x00A00000
DPAA2 DPL 0x00D00000
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000
Signed-off-by: Santan Kumar <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't
get Kconfig errors on platforms without SPL, ie sandbox (without SPL).
Signed-off-by: Tom Rini <[email protected]>
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At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.
Update existing users and move the ide driver into drivers/block since
it should not be in common/.
Signed-off-by: Simon Glass <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_HDMIDETECT
Note that we cannot do 'default y if VIDEO' because this option is only
enabled for a small subset of mx6 boards. Also this command is is not a
great implementation (it doesn't use driver model).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_HASH
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
[trini: Rework slightly, enable on some boards again]
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_FUSE
Signed-off-by: Simon Glass <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_ESBC_VALIDATE
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_ENTERRCM
Signed-off-by: Simon Glass <[email protected]>
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Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
using hardware acceleration.") created entries for CONFIG_SHA1,
CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
However, no defconfig has migrated to it. Complete the move by first
adding additional logic to various Kconfig files to select this when
required and then use the moveconfig tool. In many cases we can select
these because they are required to implement other drivers. We also
correct how we include the various hashing algorithms in SPL.
This commit was generated as follows (after Kconfig additions):
[1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
[2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
Note:
We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
because there is dependency between them.
Cc: Poonam Aggrwal <[email protected]>
Cc: Naveen Burmi <[email protected]>
Cc: Po Liu <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Shaohui Xie <[email protected]>
Cc: Chunhe Lan <[email protected]>
Cc: Chander Kashyap <[email protected]>
Cc: Steve Rae <[email protected]>
Cc: Dirk Eibach <[email protected]>
Cc: Feng Li <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Sumit Garg <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: York Sun <[email protected]>
Cc: Prabhakar Kushwaha <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Akshay Saraswat <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Jagan Teki <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <[email protected]>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <[email protected]>
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The IICDVFS(I2C) set in r8a7796.h is common in rcar-gen3.
This moves CONFIG_SYS_I2C_SH_BASE0 in rcar-gen3-base.h.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The Salvator-X can have both H3 and M3 CPU on it, drop the
select R8A7795 to allow both configurations.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add Kconfig entry for the R8A7796 RCar M3 SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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The R8A7796 r1.1 reports itself as r2.0 , add quirk into the
PRR code to fix this report.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add entry for the R8A7796 RCar M3 SoC into the CPU info table.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add entry for the R8A7795 RCar H3 SoC into the CPU info table.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Allow selecting the Gen3 SoC in preparation for RCar M3 .
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This Kconfig option is not used on any board, so drop it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Import the R8A7796 PFC and GPIO tables from the latest 3.5.3 release
from Renesas .
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Sync the PFC and GPIO tables with the latest 3.5.3 release from
Renesas . This adds ES2.0 support.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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SDIO is not supported in u-boot, there is no point in enabling mmc3.
For this purpose, add u-boot specific dtsi that this will be included
automatically while building the dtb.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add SPL support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Device tree files for Arria 10
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add misc support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add pinmux support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add sdram header file for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add system manager register struct and macros for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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Add i2c, timer and other A10 macros.
Signed-off-by: Ley Foon Tan <[email protected]>
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Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <[email protected]>
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Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan <[email protected]>
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Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.
Signed-off-by: Ley Foon Tan <[email protected]>
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