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The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <[email protected]>
Cc: Chong Huang <[email protected]>
Cc: Dimitar Penev <[email protected]>
Cc: Haitao Zhang <[email protected]>
Cc: I-SYST Micromodule <[email protected]>
Cc: M.Hasewinkel (MHA) <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Martin Strubel <[email protected]>
Cc: Peter Meerwald <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Valentin Yakovenkov <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on systems where these are located in low memory.
Add "cppcheck-suppress nullPointer" comments to silence cppcheck
where this is intentional and legal.
Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Sonic Zhang <[email protected]>
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- Add comments for watchdog event initialization.
- Make sure the writting operation to MMRs are finished.
Signed-off-by: Sonic Zhang <[email protected]>
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- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.
Signed-off-by: Sonic Zhang <[email protected]>
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- Enable hw_watchdog_init() in watchdog.h if CONFIG_HW_WATCHDOG is defined.
- Move blackfin hw watchdog driver to the generic driver folder.
- Call hw_watchdog_init() from blackfin board init code.
- Reuse macro CONFIG_WATCHDOG_TIMEOUT_MSECS
- Update README.watchdog accordingly
Signed-off-by: Sonic Zhang <[email protected]>
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Signed-off-by: Sonic Zhang <[email protected]>
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The early serial should not be configured again in initcode() for BYPASS
boot mode and in start() for the other LDR boot modes.
In BYPASS boot mode, the start up code is located in Nor flash address other
than the DRAM address defined in link script. The code embedded string can't
be addressed by its compile time symbol. Calculate it according to the flash
offset.
Signed-off-by: Sonic Zhang <[email protected]>
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Calculate the early uart clock from the system clock registers set by
the bootrom other than the predefine uboot clock macros.
Split the early baudrate setting function and the normal baudrate
setting one.
Signed-off-by: Sonic Zhang <[email protected]>
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Newer gcc versions will sometimes use a Preg when "r" constraints, but
that'll fail if we use an Ireg in the assignment. So force the code
to always use a Dreg.
This also fixes early boot crashes for older Blackfin parts when compiled
with gcc-4.5. This version ends up selecting the same register for the
input and output variables which corrupts the output assignment triggering
an exception.
P2 = 0xffe02008; /* EVT2 */
R0 = RETS;
CALL 1f;
RTN;
1: P2 = RETS; <-- BAD
RETS = R0;
[P2] = P2; <-- BAD
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Add Bf60x resume from hibernate support
Signed-off-by: Steven Miao <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
Signed-off-by: Bob Liu <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Signed-off-by: Bob Liu <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Since the serial struct declares the sizes for us, no need to hardcode
them in the accessor functions. Let the bfin_{read,write} helpers do
it for us.
Signed-off-by: Mike Frysinger <[email protected]>
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We really only need to tweak the async banks in the initcode if the
processor is booting out of it, otherwise we can wait until later
on in the CPU booting setup.
This also makes testing in the sim and early bring up over JTAG work
much smoother when the initcode gets bypassed.
Signed-off-by: Mike Frysinger <[email protected]>
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This brings CONFIG_SERIAL_MULTI support to the Blackfin on-chip UARTs.
Ends up adding only ~512bytes per additional UART.
Signed-off-by: Mike Frysinger <[email protected]>
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Signed-off-by: Mike Frysinger <[email protected]>
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We cannot rely on the syscontrol rom func to program PLL_DIV with anomaly
05000440 is in effect, so manually program the MMR when necessary.
Signed-off-by: Mike Frysinger <[email protected]>
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Older on-chip Blackfin bootroms do not create a dummy NMI handler, so set
up one ourselves when anomaly 05000219 applies.
Signed-off-by: Mike Frysinger <[email protected]>
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Signed-off-by: Mike Frysinger <[email protected]>
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Signed-off-by: Peter Tyser <[email protected]>
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