summaryrefslogtreecommitdiff
path: root/arch/microblaze/cpu
AgeCommit message (Collapse)Author
2026-01-20Merge patch series "Update linker scripts to ensure appended device tree is ↵Tom Rini
correctly aligned" Tom Rini <[email protected]> says: This series builds on top of what Beleswar Padhi did in [1]. While there's still discussion about the mkimage related parts, the linker portion appears to the reliable path forward. An alternative that I had mentioned before, and was part of previous discussions on this topic[2] is in the end I believe not reliable enough. While we can take an output file and pad it to where we think it needs to be, ultimately the linker needs to place the symbol where we want it and if that isn't where we pad to, we have a different problem. So what this series does (but each commit message elaborates on the arch-specific linker scripts being inconsistent) is make sure the linker script will place the required symbol at 8-byte alignment, and then also use an ASSERT to fail the build if this would not be true due to some unforseen event. [1]: https://lore.kernel.org/u-boot/[email protected]/ [2]: https://source.denx.de/u-boot/u-boot/-/issues/30 Link: https://lore.kernel.org/r/[email protected]
2026-01-20microblaze: Update linker scripts to ensure appended device tree is alignedTom Rini
With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains that we must have ALIGN(x) statements inside of a section to ensure that padding is included and not simply that the linker address counter is incremented. To that end, this patch: - Aligns the final section before _end (for U-Boot) or _image_binary_end (for xPL phases) by 8-bytes by adjusting the ALIGN(4) statement to be ALIGN(8) in the final section before the symbol. - Ensure that we do have alignment by adding an ASSERT so that when not aligned we fail to link (and explain why). Tested-by: Michal Simek <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2026-01-19microblaze: Fix SPL device supportMichal Simek
Extend spl_boot_list[] only when SPL has support for it. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d1c1d677b2eb4266290d31dbdf2e6e44c77a75ff.1768557507.git.michal.simek@amd.com
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <[email protected]>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-06global: Make <asm/global_data.h> include <asm/u-boot.h>Tom Rini
This follows the example of RISC-V where <asm/global_data.h> includes <asm/u-boot.h> directly as "gd" includes a reference to bd_info already and so the first must include the second anyhow. We then remove <asm/u-boot.h> from all of the places which include references to "gd" an so have <asm/global_data.h> already. Signed-off-by: Tom Rini <[email protected]>
2023-10-24microblaze: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <[email protected]> Acked-by: Michal Simek <[email protected]>
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-03microblaze: u-boot-spl.lds: Pass _image_binary_endFabio Estevam
Pass _image_binary_end to make a standard way to indicate the end of the text section in SPL. The motivation for this is to have a uniform way to handle the SPL boundary checks. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-03-13microblaze: drop remnants of manual relocOvidiu Panait
Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Reviewed-by: Michal Simek <[email protected]> Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-02-09Correct SPL uses of CPU_MICROBLAZESimon Glass
This converts 2 usages of this option to the non-SPL form, since there is no SPL_CPU_MICROBLAZE defined in Kconfig Signed-off-by: Simon Glass <[email protected]>
2023-01-27microblaze: spl: drop boot_linuxOvidiu Panait
Drop boot_linux variable as it is not assigned anywhere. Now that there is no variable controlling linux boot in spl_start_uboot(), make this function always return false when falcon mode is enabled. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-01-27microblaze: spl: wrap spl_start_uboot() in SPL_OS_BOOT ifdefsOvidiu Panait
Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled, since it is only used for falcon mode. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <[email protected]>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-24microblaze: Remove interrupt handlerMichal Simek
The primary purpose for this code was timer. By converting it to CONFIG_TIMER there is no code which uses this implementation that's why remove it. If there is a need to handle interrupts this patch can be reverted in future. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <[email protected]> Tested-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: add support for handling PVR dataOvidiu Panait
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: introduce cpuinfo structureOvidiu Panait
Introduce a minimal cpuinfo structure to hold cache related info. The instruction/data cache size and cache line size are initialized early in the boot to default Kconfig values. They will be overwritten with data from PVR/dtb if the microblaze UCLASS_CPU driver is enabled. The cpuinfo struct was placed in global_data to allow the microblaze UCLASS_CPU driver to also run before relocation (initialized global data should be read-only before relocation). gd_cpuinfo() helper macro was added to avoid volatile "-Wdiscarded-qualifiers" warnings when using the pointer directly. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]> (s/bralid/brlid/)
2022-06-24microblaze: cache: introduce flush_cache_all()Ovidiu Panait
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: introduce Kconfig options for icache/dcache sizesOvidiu Panait
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]> (s/bralid/brlid/g)
2022-06-24microblaze: cache: split flush_cache() functionOvidiu Panait
Factor out icache/dcache components from flush_cache() function. Call the newly added __flush_icache()/__flush_dcache() functions inside icache_disable() and dcache_disable(), respectively. There is no need to flush both caches when disabling a particular cache type. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: improve icache Kconfig optionsOvidiu Panait
Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: improve dcache Kconfig optionsOvidiu Panait
Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHEOvidiu Panait
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify cache handling"), but it was still used in a couple of places. Replace those occurences with CONFIG_DCACHE. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: start.S: remove unused codeOvidiu Panait
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: Add support for run time relocationMichal Simek
Microblaze is using NEEDS_MANUAL_RELOC from the beginnging. This is causing issues with function pointer arrays which need to be updated manually after relocation. Building code with -fPIC and linking with -pic will remove this limitation and there is no longer need to run manual update. By default still old option is enabled but by disabling NEEDS_MANUAL_RELOC code will be compiled for full relocation. The patch does couple of things which are connected to each other. - Define STATIC_RELA dependency to call relocate-rela to fill sections. - REMAKE_ELF was already enabled but u-boot file can't be used because sections are empty. relocate-rela will fill them and output file is u-boot.elf which should be used. - Add support for full relocation (u-boot.elf) - Add support for early relocation when u-boot.bin is loaded to different address then CONFIG_SYS_TEXT_BASE - Add rela.dyn and dynsym sections Disabling NEEDS_MANUAL_RELOC U-Boot size increased by 10% of it's original size (550kB to 608kB). Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/a845670b34925859b2e321875f7588a29f6655f9.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Create SYM_ADDR macro to deal with symbolsMichal Simek
Symbol handling depends on compilation flags. Right now manual relocation is used that's why symbols can be referenced just by name and there is no need to find them out. But when position independent code (PIC) is used symbols need to be described differently. That's why having one macro change is easier than changing the whole code. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d704e9a267c8b536452fb999111dbfbc9d652be5.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Add comment about reset locationMichal Simek
Better to add comment to explain why reset vector points all the time to origin U-Boot location. If reset happens U-Boot should start from it's origin location. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5ca6341b7487708247fe2948d7e496ea6f7c2e02.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove _start symbol handling at U-Boot startMichal Simek
Right now U-Boot runs all the time from the same address where it is loaded but going to full relocation code starting address doesn't need to be fixed and can be simply discovered from reading PC register. That's why use r20 to get PC address and subtract offset from the beginning to get starting address. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/044b727c33dfbe662f68512d0da0775a4805f360.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove code around r20 in relocate_code()Michal Simek
r20 is not used that's why remove logic around it. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/1b32bab5c050d099b2f6d49bc4896322ed03d788.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Optimize register usage in relocate_codeMichal Simek
There are additional operations which can be done simpler that's why improve logic around relocation address r7 handling and _start symbol. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c8b60f72f1605c2ba6b4b7be1893d7e6ec3d8597.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Change stack protection address to new stack addressMichal Simek
SLR low address is still setup to 0 that's why only high limit should be updated. STACK_SIZE macro is present and could be possible used for low address alignment but it is not done by this patch. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c00cb843df848703b760a65934ed3ce31fafcf19.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Separate code end substractionMichal Simek
Follow up patch will convert symbol handling that's why it is necessary to separate logic around symbols to special instruction. It adds 4B for new instruction but it is worth to do it to have code ready for for full relocation. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/030863fa9a9c1ca0a9b082fe498522da09189fbc.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix typo in exception.cMichal Simek
Trivial fix. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c4ede6dc738c5bd7c518f3bb2c9410b15c102e20.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove CONFIG_TEXT_BASE from codeMichal Simek
Use symbol instead macro to find where U-Boot starts. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d5d4c201bee6171e85b47783d916387d84db0456.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix early stack allocationMichal Simek
CONFIG_SYS_INIT_SP_OFFSET macro place stack to TEXT_BASE - SYS_MALLOC_F_LEN but there is no reason to do it now because board_init_f_alloc_reserve() returns exact location where stack should be. That's why stack location is calculated at run time and there is no need to hardcode it via macro. This change will help with placing U-Boot to any address. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/e9aee69646e022fd8a96cbee2d2a07ab81fb6e05.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix stack protection behaviorMichal Simek
When U-Boot starts stack protection can be already enabled that's why setup the lowest possible SLR value which is address 0. And the highest possible stack in front of U-Boot. That's why you should never load U-Boot to the beginning of DDR. There must be some space reserved. Code is using this location for early malloc space, early global data and stack. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/86b9748bad12142659804d6381bc6bbf20be44f1.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Switch absolute branches to relativeMichal Simek
There is no reason to use absolute branches and use just relative. This change helps with moving binary to different location and start it from there. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/83a5103b85c1c2220cd3ab4d5365169c6660e40a.1655299267.git.michal.simek@amd.com
2022-06-23linker_lists: Rename sections to remove . prefixAndrew Scull
Rename the sections used to implement linker lists so they begin with '__u_boot_list' rather than '.u_boot_list'. The double underscore at the start is still distinct from the single underscore used by the symbol names. Having a '.' in the section names conflicts with clang's ASAN instrumentation which tries to add redzones between the linker list elements, causing expected accesses to fail. However, clang doesn't try to add redzones to user sections, which are names with all alphanumeric and underscore characters. Signed-off-by: Andrew Scull <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-06-06Convert CONFIG_SPL_STACK to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SPL_STACK Signed-off-by: Tom Rini <[email protected]>
2022-02-15microblaze: exception: fix unaligned data access register maskOvidiu Panait
The correct mask for getting the source/destination register from ESR in the case of an unaligned access exception is 0x3E0. With this change, a dummy unaligned store produces the expected info: """ >> swi r5, r0, 0x111 ... Hardware exception at 0x111 address Unaligned data access exception Unaligned word access Unaligned store access Register R5 Return address from exception 0x7f99dfc ### ERROR ### Please RESET the board ### """ Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-02-15microblaze: exception: move unaligned access printfs inside switch caseOvidiu Panait
The unaligned access messages are only valid in the case of an unaligned data access exception. Do not print them for other types of hw exceptions. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-02-15microblaze: exception: fix return address for delay slot exceptionsOvidiu Panait
According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37): """ If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17. """ Adjust the code to print the proper return address for delay slot exceptions. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-02-15microblaze: exception: fix delay slot exception handlingOvidiu Panait
The switch statement in _hw_exception_handler() only covers the rightmost 5 bits that encode the exception cause: switch (state & 0x1f) { ... } For this reason, the "0x1000" case will never be reached, because the 13th bit was zeroed out. To fix this, move delay slot exception handling before the switch statement (delay slot (DS) bit in Exception Status Register is independent of the exception cause (EC)). Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-02-15microblaze: exception: migrate MICROBLAZE_V5 to KconfigOvidiu Panait
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only covers delay slot exception support. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-02-15microblaze: exception: move privileged instruction exception out of v5 ifdefOvidiu Panait
The privileged instruction exception seems to have been introduced in microblaze v7.00 along with MMU support, so having it wrapped in MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all recent microblaze versions support it. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-12 07:15:48 +0000