| Age | Commit message (Collapse) | Author |
|---|
|
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.
Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Daniel Schwierzeck <[email protected]>
|
|
Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Paul Burton <[email protected]>
|
|
The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.
Signed-off-by: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
|
|
Use "obj-$(CONFIG_FOO) += foo/" where it is possible.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
|
|
Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
|
|
Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available. But this doesn't always work.
We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources. And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.
With this change, each $(CPU)/ directory can have its own timer code.
Signed-off-by: Shinya Kuribayashi <[email protected]>
|
|
Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Thomas Lange <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
|
|
IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
|
|
All current CPUs and SoCs are based on MIPS32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other MIPS architectures like MIPS64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
subdirectory. All MIPS32 boards have to use mips32 as config switch
in board.cfg.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Thomas Lange <[email protected]>
Cc: Vlad Lungu <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
|
