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For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.
Signed-off-by: Minda Chen <[email protected]>
Tested-by: E Shattow <[email protected]>
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Separate setjmp.h into an architecture independent part and an architecture
specific part. This simplifies moving from using struct jmp_buf_data
directly to using type jmp_buf in our code which is the C compliant way.
Reviewed-by: Jerome Forissier <[email protected]>
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Enhance the existing extension probing mechanism by adding support for
more extensions and probing using the "riscv,isa" property. This patch
is ported from the latest upstream linux.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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If we take an exception before u-boot is relocated, there's a good
chance we will end up in an endless loop of exceptions because resume is
invalid until after relocation.
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add insn-def.h which is similar to that in linux and contains the macros
to generate any instruction of type 'I' using the assembler's .insn
directive.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The SBI 3.0 specification [1] adds the following extensions:
* Firmware Features Extension
* Message Proxy Extension
Let the sbi command detect their availability.
The Firmware Features Extension is already implemented in OpenSBI.
Correct the text for the DBTR extension and move it to the same position
as in the specification.
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/vv3.0-rc1/riscv-sbi.pdf
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Prepare v2024.10-rc5
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Add driver for AST2700 to initialize DRAM in SPL.
This patch also refactors the Kconfig dependency of
Aspeed DRAM drivers as some of them are shared among
the file structures of RV and ARM ISAs.
Signed-off-by: Chia-Wei Wang <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Define and parse the header of the First Mutable Code (FMC)
of AST2700 SoCs at runtime phase.
The FMC header contains the information to load prebuilt binaries
required for device initialization such as DRAM and VGA.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.
This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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These seem to be missing, and trying to build fastboot cmd without
them is causing errors due to these being missing.
Signed-off-by: Maxim Kochetkov <[email protected]>
Tested-by: E Shattow <[email protected]
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The EEPROM provides information about the size of the eMMC.
Provide a new function get_mmc_size_from_eeprom() to read it.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: E. Shattow <[email protected]>
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Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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OpenSBI has implemented the Supervisor Software Events Extension.
Allow detecting it in the sbi command.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Export a function get_product_id_from_eeprom() to read the product ID.
This value can be used for fixing up the device-tree on JH7110 based
products.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Detect and show if the SBI implements the Debug Trigger Extension.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
Signed-off-by: Vincent Chen <[email protected]>
Co-developed-by: Nylon Chen <[email protected]>
Signed-off-by: Nylon Chen <[email protected]>
Co-developed-by: Zong Li <[email protected]>
Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add fields for the location of ACPI tables to the global data.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Andes CPU supports cache and TLB ECC.
Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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In most cases, the architecture global data currently makes use of
assorted linux types, but does not include <linux/types.h> to provide
them. Add <linux/types.h> instead of relying on indirect inclusion.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Change type of address parameter from int* to volatile void* for
{read,write}s{b,w,l}() functions and add const qualifier for reads. This
is done to keep function signatures in sync with asm-generic/io.h and
other platforms.
Signed-off-by: Igor Prusov <[email protected]>
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Add defines for {read,write}s{b,w,l} functions to make asm-generic/io.h
aware of them.
Signed-off-by: Igor Prusov <[email protected]>
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This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add gpio.h header file that includes JH7110 helper macros. The file is
imported from StarFive github[1] with small changes such as alignment.
[1]: https://github.com/starfive-tech/u-boot
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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Remember where these end up so that we can pass this information on to
the EFI layer.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The DBCN extension provides a Console Write Byte call.
Implement function sbi_dbcn_write_byte to invoke it.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Very few of the existing event-spy records use the arguments they are
passed. Update them to use a simple spy instead, to simplify the code.
Where an adaptor function is currently used, remove it where possible.
Signed-off-by: Simon Glass <[email protected]>
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The SBI specification v2.0-rc2 defines new extensions:
* Nested Acceleration Extension (NACL)
* Steal Time Accounting (STA)
Allow the sbi command to display these.
Add missing implementation IDs.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h. This file does not exist for the RISC-V architecture
and thus code compilation fails when using this driver on RISC-V
Create an empty include file.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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These seem to be missing, and trying to build ubifs without them
is causing errors due to these being missing.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add implementations of the local_irq_{save,restore} macros so that
<asm/atomic.h> can be used with riscv.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add a link from <asm/atomic.h> to the generic one to allow
things like ubifs to be built. This can be extended with
riscv AMO ops at a later date.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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OpenSBI already implements some extensions that are not ratified yet:
* Debug Console Extension (DBCN)
* System Suspend Extension (SUSP)
* Collaborative Processor Performance Control Extension (CPPC)
Allow the sbi command to display these.
Provide the FID definitions of the Debug Console Extension. We can use that
extension for an early debug console driver.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add support to load the next stage image from an NVMe disk which may
be formatted as an EXT or FAT filesystem.
Signed-off-by: Mayuresh Chitale <[email protected]>
[trini: Drop hunk changing disk/part.c as that breaks other users]
Signed-off-by: Tom Rini <[email protected]>
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As part of various code clean-ups we have on occasion missed removing
unused header files. None of these files are referenced anywhere else
at this point.
Signed-off-by: Tom Rini <[email protected]>
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Replace NDS32 with RISC-V in the comments.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Tested-by: Conor Dooley <[email protected]>
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As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Kautuk Consul <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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