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AgeCommit message (Expand)Author
2023-10-04riscv: andesv5: Prefer using the generic RISC-V timer driver in S-modeYu Chien Peter Lin
2023-10-04configs: andes: add vender prefix for target nameRandolph
2023-10-04riscv: enable CONFIG_DEBUG_UART by defaultHeinrich Schuchardt
2023-10-04riscv: bootstage: correct bootstage_report guardChanho Park
2023-10-02Merge branch 'next'Tom Rini
2023-09-26riscv: set fdtfile on VisionFive 2Heinrich Schuchardt
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
2023-09-22Record the position of the SMBIOS tablesSimon Glass
2023-09-20riscv: dts: starfive: generate u-boot-spl.bin.normal.outHeinrich Schuchardt
2023-09-20riscv: set fdtfile on VisionFive 2Heinrich Schuchardt
2023-09-06riscv: Correct event usage for riscv_cpu_probe/setupTom Rini
2023-09-06riscv: Rework riscv_cpu_probe for current event macrosTom Rini
2023-09-05risc-v: implement DBCN write byteHeinrich Schuchardt
2023-09-05riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INITShengyu Qu
2023-09-05riscv: jh7110: enable riscv,timer in the device treeTorsten Duwe
2023-09-04Merge tag 'v2023.10-rc4' into nextTom Rini
2023-08-31event: Convert existing spy records to simpleSimon Glass
2023-08-22riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callbackChanho Park
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt
2023-08-10riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USEShengyu Qu
2023-08-10riscv: Add SPL_ZERO_MEM_BEFORE_USE implementationShengyu Qu
2023-08-10riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USEShengyu Qu
2023-08-10riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZEMinda Chen
2023-08-10riscv: dts: starfive: Enable pcie0 dts nodeMinda Chen
2023-08-10cmd/sbi: display new extensionsHeinrich Schuchardt
2023-08-02acpi: Add missing RISC-V acpi_table headerHeinrich Schuchardt
2023-08-02riscv: dts: starfive: Enable PCIe host controllerMason Huo
2023-07-24riscv: define a cache line size for the generic CPUHeinrich Schuchardt
2023-07-24riscv: dts: jh7110: Add clock source from PLLXingyu Wu
2023-07-24riscv: dts: jh7110: Add PLL clock controller nodeXingyu Wu
2023-07-24riscv: setup per-hart stack earlierBo Gan
2023-07-12riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A boardYixun Lan
2023-07-12riscv: t-head: licheepi4a: initial support addedYixun Lan
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
2023-07-12riscv: clint: Update the sifive clint ipi driver to support aclintBin Meng
2023-07-12ram: starfive: Read memory size information from EEPROMYanhong Wang
2023-07-12riscv: dts: starfive: Add support eeprom device tree nodeYanhong Wang
2023-07-12eeprom: starfive: Enable ID EEPROM configurationYanhong Wang
2023-07-12riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3BYanhong Wang
2023-07-12riscv: dts: jh7110: Add ethernet device tree nodesYanhong Wang
2023-07-06riscv: andes_plicsw: Fix IPI during OpenSBI invocationYu Chien Peter Lin
2023-07-06riscv: dts: sync mpfs-icicle devicetree with linuxConor Dooley
2023-07-06riscv: dts: drop microchip from dts filenamesConor Dooley
2023-07-06riscv: define test_and_{set,clear}_bit in asm/bitops.hBen Dooks
2023-07-06riscv: implement local_irq_{save,restore} macrosBen Dooks
2023-07-06riscv: add generic link for <asm/atomic.h>Ben Dooks
2023-07-06cmd/sbi: display new extensionsHeinrich Schuchardt
2023-07-05Merge tag 'v2023.07-rc6' into nextTom Rini
2023-06-27riscv: Fix alignment of RELA sections in the linker scriptsBin Meng
2023-06-19common: spl: Add spl NVMe boot supportMayuresh Chitale