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Simon Glass <[email protected]> says:
Each arch does something slightly different before booting the OS. Some
archs even do different things depending on the CPU type.
It is quite hard to know what actually happens in the final milliseconds
before the OS boot.
This series attempts to start cleaning up U-Boot in this area.
The basic intent is to create a new bootm_final() function which can be
called by all archs. It provides some flags for a couple of necessary
variations but otherwise it is generic.
All architectures are converted over to use this new function.
board_quiesce_devices() is moved into bootm_final() so that all archs
benefit from it.
This series fixes a bug in device_remove() is fixed where removing a
parent with specialised flags (e.g. DM_REMOVE_ACTIVE_ALL) could leave
children activated, since they do not match the flags. This fixes is
needed to avoid bootm_final() causing test failures on sandbox.
Future work could take this a little further:
- Convert EFI loader to use the same function
- Improve comments for cleanup_before_linux() across architectures
- Support fake-run tracing on all archs
Link: https://lore.kernel.org/r/[email protected]
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The RISC-V announce_and_cleanup() duplicates the common pre-boot
steps. Replace it with a call to bootm_final().
Move board_quiesce_devices() into bootm_final() so it is available to
all architectures. Drop the RISC-V weak definition and header
declaration since the generic one in bootm.h is used instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Bring U-Boot support for the BeagleV-Fire by adding a device tree and
supporting board files etc.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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pcb_revision is stored in the pcb_revision field of ATOM4. Correct it.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.
Reviewed-by: Heinrich Schuchardt <[email protected]>
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Hal Feng <[email protected]>
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Directly return the DDR size instead of the field of 'DxxxExxx'.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.
Reviewed-by: Heinrich Schuchardt <[email protected]>
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Hal Feng <[email protected]>
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Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.
MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
So we don't need CONFIG_(SPL_)ACLINT either.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Conor Dooley <[email protected]>
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Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.
Signed-off-by: Nick Hu <[email protected]>
Signed-off-by: Jimmy Ho <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <[email protected]> #TI boards
Acked-by: Yao Zi <[email protected]> #TH1520
Signed-off-by: Peng Fan <[email protected]>
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With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end (for U-Boot) or _image_binary_end
(for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final
section before the symbol.
- Remove a now-spurious '. = ALIGN(x);' statement that was intended to
provide the above alignments.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The following functions are provided:
Count leading zero bits
* int __clzsi2 (unsigned int a)
* int __clzdi2 (unsigned long a)
* int __clzti2 (unsigned long long a)
Count trailing zero bits
* int __ctzsi2 (unsigned int a)
* int __ctzdi2 (unsigned long a)
* int __ctzti2 (unsigned long long a)
Signed-off-by: Heinrich Schuchardt <[email protected]>
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There are multiple boards that use the PolarFire SoC, so extract
the Kconfig sections that are determined at a CPU level from the board
Kconfigs now that we have a CPU Kconfig.
Signed-off-by: Conor Dooley <[email protected]>
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PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Updated DTS and configuration files to set the default baud rate from 38400 to 115200.
Signed-off-by: Che-Wei Chuang <[email protected]>
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Add '\n' to the end of the warning message.
Besides, if we enable console record utility,
missing the '\n' causes the console_record_readline
fail to recognize the end of string.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Anshul Dalal <[email protected]> says:
Hi all,
We currently make use of CMD_BOOTI and CMD_BOOTZ in the SPL boot flow in
falcon mode, this isn't correct since all CMD_* configs are only meant
for U-Boot proper and not the SPL.
Therefore this patch set adds new LIB_BOOT[IMZ] configs that allow for
more granular selection of their respective compilation targets.
Additionally, this also allows us to more easily disable support for
raw images from secure falcon mode (SPL_OS_BOOT_SECURE) by doing the
following:
config LIB_SPL_BOOTI
...
depends on SPL_OS_BOOT && !SPL_OS_BOOT_SECURE
...
Link: https://lore.kernel.org/r/[email protected]
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Using CMD_* configs from spl doesn't make logical sense. Therefore
this patch replaces the checks for CMD_BOOTx with newly added library
symbols LIB_BOOT[IMZ] and SPL_LIB_BOOT[IMZ] which are enabled by their
respective CMD_* or SPL_* counterparts.
On platforms with non-secure falcon mode, SPL_BOOTZ is enabled by
default for 32-bit ARM systems and SPL_BOOTI is enabled by default for
64-bit ARM and RISCV.
The respective C files (image.c/zimage.c) are compiled based on library
symbols $(PHASE_)LIB_BOOTx instead which are in turn selected by both
CMD_BOOTx and SPL_BOOTx as required.
Signed-off-by: Anshul Dalal <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Prune overrides of upstream jh7110.dtsi now that the required nodes are
available through the devicetree-rebasing subtree.
Signed-off-by: E Shattow <[email protected]>
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In contrast to some other Allwinner SoCs, there is no difference between
the DTs for the Allwinner T113-s3 SoC (sun20i) between the U-Boot and the
Linux kernel repository.
Remove the old copies of the T113-s3 related .dts and .dtsi files, and
switch the whole SoC (represented by just one board) over to use
OF_UPSTREAM.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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This reverts commit a681cfecb4346107212f377e2075f6eb1bdc6a2b.
It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.
Reported-by: E Shattow <[email protected]>
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Yao Zi <[email protected]>
Acked-by: E Shattow <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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to defconfig
Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list
DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file.
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on
automatic inclusion of jh7110-u-boot.dtsi
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
"riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and
bootph-pre-ram hints now upstream since devicetree-rebasing v6.16).
In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include
by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order.
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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This patch remove the unused macro DRAM_BASE.
Signed-off-by: Greentime Hu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Make all Icicle Kit files generic. This supports the addition of
upcoming support for other MPFS boards.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add an alternative implementation that use Zalrsc extension only for
HART lottery and SMP locking to support SMP on cores without "Zaamo"
extension available. The Zaamo implementation is still prioritized if
both of them are available, since it takes fewer instructions.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Ratified on Apr. 2024, the original RISC-V "A" extension is now split
into two separate extensions, "Zaamo" for atomic operations and "Zalrsc"
for load-reserved/store-conditional instructions.
For now, we've already seen real-world designs implement the Zalrsc
extension only[2]. As U-Boot mainly runs with only one HART, we could
easily support these designs by not using AMO instructions in the
hard-written assembly if necessary, for which this patch introduces two
new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc".
Note that even with this patch, "A" extension is specified in the ISA
string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is
available, since they're only recognized with a quite recent version of
GCC/Clang. The compiler usually doesn't automatically generate atomic
instructions unless the source explicitly instructs it to do so, thus
this should be safe.
Link: https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126 # [1]
Link: https://lore.kernel.org/u-boot/[email protected]/ # [2]
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards
to use the correct upstream devicetree paths.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Introduce the initial device tree support for Andes Voyager board.
We will convert to OF_UPSTREAM once the patch series for kernel is merged.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The Voyager is Andes' first RISC-V development board.
It is built around Qilai SoC,
which includes Andes AX45MP quad-core cluster.
Introduce the Kconfig entry for the Voyager board.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Properties didn't match dt binding that's why should be fixed.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Test for big-endian either via __RISCVEB__ which migth be
rather old, or check the BYTE_ORDER if the compiler defines
it (which should be any modern gcc like v12)
Signed-off-by: Ben Dooks <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Add support to build code big-endian if the board supports
it. Updates the makefile to pass the correct compiler and
elf flags.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.
This patch sets them up for efficient operation and satisfying
requirements of an SMP system.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.
As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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This will allow arch(s) that use device tree blobs to pad the end of the
device tree so they can be modified by board files at run time. This will
help prevent errors such as FDT_ERR_NOSPACE from occurring.
Signed-off-by: Eric Schikschneit <[email protected]>
[trini: Change default order so that X86 && EFI_APP works correctly]
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Rasmus Villemoes <[email protected]> says:
There's really no reason for the gd pointer to have the volatile
qualifier.
In fact, I claim that it's completely unnecessary and just pessimizes
code generation and forces ugly casts in lots of places. For example,
see the casts in drivers/core/tag.c where elements are added to
gd->dm_taglist, or a helper such as cyclic_get_list() that should not
be needed.
Also, it is what ends up standing in the way of an otherwise
innocent code cleanup of list.h:
https://lore.kernel.org/u-boot/20250522165656.GB2179216@bill-the-cat/
Note that riscv, x86 as well as arm64 with LTO enabled has not had
this volatile qualifier, so it's unlikely there's any generic code
that depends on it.
Link: https://lore.kernel.org/r/[email protected]
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It's slightly ironic that riscv at very first had the gd pointer
volatile qualified [6020faf62c3 ("riscv: nx25: include: Add header
files to support RISC-V")], removed that back in 2018
[40717eb849c ("riscv: checkpatch: Fix use of volatile")], and then in
2020 this helper was added [6b9966e1aa3 ("riscv: define function
set_gd()")] which needlessly had volatile in the prototype.
Signed-off-by: Rasmus Villemoes <[email protected]>
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This function is currently a misnomer at times as we have cases where it
passes arguments to the image. In preparation for making that be a more
common case rename this function to jump_to_image(...). In order to do
this, rename jump_to_image in board_init_r(...) to jumper so that we do
not have a conflict.
Signed-off-by: Simon Glass <[email protected]>
[trini: Reword the commit message, adding missing cases of
jump_to_image_no_args()]
Signed-off-by: Tom Rini <[email protected]>
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