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Update the link script to drop this code when not needed. This is only done
for two architectures at present.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.
U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.
In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust the existing implementation to use the new common SDRAM init code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add a function to set the ID in the IOAPIC.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <[email protected]>
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Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.
The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Add a driver for the broadwell low-power platform controller hub.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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This adds the broadwell architecture, with the CPU driver and some useful
header files.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Bin Meng <[email protected]>
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Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <[email protected]>
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This same name is used in USB. Add a prefix to distinguish it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).
Add a new header file for these registers, and move MCH into it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This code is used on several Intel CPUs. Move it into a common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This does not need to be modified at run-time, so make it const.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Use this new function in places where it simplifies the code.
Signed-off-by: Simon Glass <[email protected]>
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This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <[email protected]>
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Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)
Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Minkyu Kang <[email protected]>
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There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Drop legacy PCI APIs usage in pci_assign_irqs() as well.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.
To fix this, manually remove these two devices.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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So far disable_igd() does not have any return value, but we may need
that in the future.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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