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path: root/arch/x86/cpu
AgeCommit message (Expand)Author
2015-08-05x86: Add support for U-Boot as an EFI applicationBen Stoltz
2015-08-05x86: Tidy up a few minor issues with interruptsSimon Glass
2015-08-05x86: Add some missing global_data declarations in files that use gdSimon Glass
2015-08-05x86: Tidy up the 64-bit calling codeSimon Glass
2015-08-05x86: Tidy up global_data flagsSimon Glass
2015-08-05x86: Use CR0 constants in CPU initSimon Glass
2015-08-05x86: Add various minor tidy-ups to the 32-bit startup codeSimon Glass
2015-08-05x86: bayleybay: Configure PCI IRQBin Meng
2015-07-28x86: qemu: Turn on PCIe ECAM address range decoding on Q35Bin Meng
2015-07-28x86: qemu: Enable writing MP tableBin Meng
2015-07-28x86: Allow cpu-x86 driver to be probed for UPBin Meng
2015-07-28x86: qemu: Enable I/O APIC chip select on PIIX3Bin Meng
2015-07-28x86: Convert to use driver model pci on queensbay/crownbayBin Meng
2015-07-28x86: pci: Do not assign irq 0 to pci deviceBin Meng
2015-07-28x86: pci: Assign pci irqs to all functionsBin Meng
2015-07-28x86: Enable DM RTC support for all x86 boardsBin Meng
2015-07-28x86: Change pci option rom area MTRR setting to cacheableBin Meng
2015-07-28x86: Simplify architecture defined exception handling in irq_llsr()Bin Meng
2015-07-28x86: Display correct CS/EIP/EFLAGS when there is an error codeBin Meng
2015-07-27Kill unneeded #include <linux/kconfig.h>Masahiro Yamada
2015-07-14dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass
2015-07-14dm: x86: minnowmax: Move PCI to use driver modelSimon Glass
2015-07-14x86: pci: Tidy up the generic x86 PCI driverSimon Glass
2015-07-14x86: queensbay: Change CPU_ADDR_BITS to 32Bin Meng
2015-07-14x86: Setup fixed range MTRRs for legacy regionsBin Meng
2015-07-14x86: queensbay: Change PCIe root ports' interrupt routingBin Meng
2015-07-14x86: Remove inline for lapic access routinesBin Meng
2015-07-14x86: Add I/O APIC register access routinesBin Meng
2015-07-14x86: Reduce PIRQ routing table sizeBin Meng
2015-07-14x86: Ignore function number when writing PIRQ routing tableBin Meng
2015-07-14x86: Write correct bus number for the irq routerBin Meng
2015-07-14x86: Clean up lapic codesBin Meng
2015-07-14x86: Move lapic_setup() call into init_bsp()Bin Meng
2015-07-14x86: Move MP initialization codes into a common placeBin Meng
2015-07-14x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng
2015-07-14x86: dm: Clean up cpu driversBin Meng
2015-07-14x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng
2015-07-14x86: fsp: Load GDT before calling FspInitEntryBin Meng
2015-07-14x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng
2015-06-04x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford
2015-06-04x86: qemu: Implement PIRQ routingBin Meng
2015-06-04x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng
2015-06-04x86: coreboot: Fix cosmetic issuesBin Meng
2015-06-04x86: qemu: Adjust VGA initializationBin Meng
2015-06-04x86: qemu: Enable legacy IDE I/O ports decodeBin Meng
2015-06-04x86: qemu: Turn on legacy segments decodeBin Meng
2015-06-04x86: Do sanity test on pirq table before writingBin Meng
2015-06-04x86: quark: Implement PIRQ routingBin Meng
2015-06-04x86: Refactor PIRQ routing supportBin Meng
2015-06-04x86: qemu: Add graphics supportBin Meng
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