summaryrefslogtreecommitdiff
path: root/arch/x86
AgeCommit message (Expand)Author
2019-12-15x86: Set the DRAM banks to reflect real locationSimon Glass
2019-12-15x86: Move fsp_prepare_mrc_cache() to fsp1 directorySimon Glass
2019-12-15x86: Don't export mrccache_update()Simon Glass
2019-12-15x86: Add mrccache support for a 'variable' cacheSimon Glass
2019-12-15x86: Update mrccache to support multiple cachesSimon Glass
2019-12-15x86: Tidy up error handling in mrccache_save()Simon Glass
2019-12-15x86: Add a new global_data member for the cache recordSimon Glass
2019-12-15x86: Adjust mrccache_get_region() to support get_mmap()Simon Glass
2019-12-15x86: Adjust mrccache_get_region() to use livetreeSimon Glass
2019-12-15x86: Correct mrccache find_next_mrc_cache() calculationSimon Glass
2019-12-15x86: Reduce mrccache record alignment sizeSimon Glass
2019-12-15x86: Define the SPL image startSimon Glass
2019-12-15x86: Move UCLASS_IRQ into a separate fileSimon Glass
2019-12-15x86: Drop unnecessary interrupt code for TPLSimon Glass
2019-12-15x86: Drop unnecessary cpu code for TPLSimon Glass
2019-12-15x86: timer: use a timer base of 0Simon Glass
2019-12-15x86: spi: Add helper functions for Intel Fast SPISimon Glass
2019-12-15i2c: designware: Avoid using static dataSimon Glass
2019-12-08x86: simplify ljmp to 32-bit codeMasahiro Yamada
2019-12-08x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada
2019-12-02common: Move board_get_usable_ram_top() out of common.hSimon Glass
2019-12-02common: Move enable/disable_interrupts out of common.hSimon Glass
2019-12-02common: Move interrupt functions into a new headerSimon Glass
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass
2019-12-02common: Move checkcpu() out of common.hSimon Glass
2019-11-03x86: Quieten TPL's jump_to_image_no_args()Simon Glass
2019-11-03x86: Don't print CPU info in TPLSimon Glass
2019-11-03x86: Move CPU init to before spl_init()Simon Glass
2019-11-03x86: Add a CPU init function for TPLSimon Glass
2019-11-03x86: tpl: Add a fake PCI busSimon Glass
2019-11-03x86: spl: Support init of a PUNITSimon Glass
2019-11-03x86: timer: Use a separate flag for whether timer is initedSimon Glass
2019-10-15binman: x86: Separate out 16-bit reset and init codeSimon Glass
2019-10-11x86: Reduce resetvec sizeSimon Glass
2019-10-11x86: Drop RESET_SEG_SIZESimon Glass
2019-10-11x86: Drop RESET_BASESimon Glass
2019-10-11x86: Update Kconfig options for FSP1Simon Glass
2019-10-11x86: Add a function to find the size of an mrccache recordSimon Glass
2019-10-11x86: Panic when SPL or TPL failSimon Glass
2019-10-08x86: Use mtrr_commit() with FSP2Simon Glass
2019-10-08x86: cpu: Don't include the cpu driver in TPLSimon Glass
2019-10-08x86: Add a function to set variable MTRRsSimon Glass
2019-10-08x86: Refactor mtrr_commit() to allow for shared codeSimon Glass
2019-10-08x86: Allow the PCH and LPC uclasses to work with of-platdataSimon Glass
2019-10-08x86: Add new common CPU functions for turbo/burst modeSimon Glass
2019-10-08x86: Tidy up some duplicate MSR definesSimon Glass
2019-10-08x86: Add common functions for TDP and perf controlSimon Glass
2019-10-08x86: Use a common bus clock for Intel CPUsSimon Glass
2019-10-08x86: Add a common function to set CPU thermal targetSimon Glass
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-15 23:31:49 +0000