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Port from Linux v6.7-rc4. Should not hurt U-Boot but makes diffing
easier and allows referencing node names in board dts.
Signed-off-by: Alexander Dahl <[email protected]>
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Required for using the new DM based atmel nand driver.
Ported from Linux v6.7-rc4.
Signed-off-by: Alexander Dahl <[email protected]>
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Nodes are ordered by register offset.
Fixes: 56246d1e8705 ("ARM: dts: at91: sama5: Add the sfr node")
Signed-off-by: Alexander Dahl <[email protected]>
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Roger Quadros <[email protected]> says:
Hi,
This series fixes USB operation on k3-j721e based boards.
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Without correct SERDES MUX and Lane control settings
USB0 will be broken. Set the MUX and Lane control devices
to be auto probed so they are configured correctly.
Signed-off-by: Roger Quadros <[email protected]>
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Without correct SERDES MUX and Lane control settings
USB0 will be broken. Set the MUX and Lane control devices
to be auto probed so they are configured correctly.
Fixes: 69b19ca67bcb ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Signed-off-by: Roger Quadros <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
Add CMDLINE dependecy for CMD_STM32KEY
STM32MP1:
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Set stdio to serial on DH STM32MP15xx DHSOM
Fix reset for usart1 in scmi configuration
STM32MP2:
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Add BSEC and OTP support for STM32MP25
Fix CONFIG_STM32MP25X flag usage
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"#if" was used instead of "#ifdef"
Fixes: 01a701994b05 ("stm32mp2: initial support")
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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We cannot use stm32key commands without CONFIG_CMDLINE so add the
required condition.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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- A number of OS boot related cleanups, a number of TI platform
fixes/cleanups, SMBIOS fixes, tweak get_maintainers.pl to report me
for more places, fix the "clean the build" pytest and add a bootstage
pytest, fix PKCS11 URI being omitted in some valid cases, make an iommu
problem easier to debug on new platforms, nvme and pci improvements,
refactor image-host code a bit, fix a typo in env setting, add a missing
dependency for CMD_LICENSE, and correct how we call getchar() in some
places.
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CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.
Signed-off-by: Simon Glass <[email protected]
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Activate the command stboard for stm32mp25 STMicroelectronics boards,
add the default used OTP identifier and the associated board identifier:
- stm32mp25xx-ev1 = MB1936
- stm32mp25xx-dk = MB1605
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Change OTP number to 364 for STM32MP25 as it is done in bsec driver.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add a function setup_mac_address() to update the MAC address from the
default location in OTP for stm32mp2 platform.
The max number of OTP for MAC address is increased to 8 for STM32MP25,
defined with get_eth_nb() and checked in setup_mac_address.
The MAC address FF:FF:FF:FF:FF:FF, the broadcast ethaddr, is a invalid
value used for unused MAC address slot in OTP, for example for board
with STM32MP25x part number allows up to 5 ethernet ports but it is not
supported by the hardware, without switch; the associated variable
"enetaddr%d" is not created.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add support of serial number for stm32mp25, gets from OTP with BSEC driver.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Add a new file soc.c for common functions between stm32mp1 and stm32mp2
family and move print_cpuinfo() in this new file.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Add support of BSEC for STM32MP25x family to access OTP.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add driver data in BSEC driver to test presence of OP-TEE TA,
mandatory for STM32MP13 family and prepare the support of new device
with more OTP than 95.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add chip revision B support for STM32MP25, for displaying it in trace.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Yann Gautier <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add BSEC support to STM32MP25 SoC family with SoC information:
- RPN = Device part number (BSEC_OTP_DATA9)
- PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122)
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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In SCMI configuration, usart1 is secure, so all its resources are secured
(clock and reset) and can't be set/unset by non-secure world but by OP-TEE.
Fixes: 6cccc8d396bf ("ARM: dts: stm32: add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)")
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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arch_cpu_init is already returning 0 in its weak definition in
common/board_f.c so let's just remove the file entirely since nothing
else is done in it.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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Remove leftover import and global data ptr from files since they aren't
used anymore.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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BOOT_DEVICE_* is set by spl_node_to_boot_device() depending on the block
device number associated with the MMC device the SPL used to load U-Boot
proper from. It is NOT related to the mmc alias in the Device Tree.
For SPI flashes, all SPI flashes will return BOOT_DEVICE_SPI so there's
currently no way to know from which one the SPL loaded U-Boot proper
from. Therefore, let's just find the first valid candidate in
/chosen/u-boot,spl-boot-order that is a SPI flash and return that path.
This is a best effort.
While the original implementation may have worked, using the exact same
mechanism but in inverted fashion makes it less likely to have
surprising corner-cases or side-effects.
A nice side-effect is that all existing and future Rockchip SoCs now
automatically have their /chosen/u-boot,spl-boot-device set.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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All SoCs are susceptible to wanting to know which storage medium was
used to load U-Boot SPL. So instead of reimplementing the same functions
in SoCs over and over again (here just rk3399 and px30 but rk3588 is
coming), let's just put all this in common into spl-boot-order.c
allowing to support a new SoC just by defining the spl_boot_devices
array in the appropriate SoC file.
Note that spl_perform_fixups() now calls spl_image_fdt_addr() to get the
address of the fdt instead of directly reading the
spl_image_info->fdt_addr member, because that member is not guaranteed
to be present (guarded with compile flags). This is essential because we
move the logic away from px30 and rk3399 which had those compile flags
enabled to code run for all Rockchip SoCs.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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In preparation of moving spl_perform_fixups to spl-boot-order.c, let's
simplify the logic around mapping the BOOT_DEVICE_x enum index to a DT
node by using an instantiated array of chars instead of creating a new
data structure on the fly.
This will make it easier to factor out the code handling the SPL boot
medium detection by having spl_decode_boot_device common to all SoCs.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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In preparation of moving spl_perform_fixups to spl-boot-order.c, let's
simplify the logic around mapping the BOOT_DEVICE_x enum index to a DT
node by using an instantiated array of chars instead of creating a new
data structure on the fly.
This will make it easier to factor out the code handling the SPL boot
medium detection by having spl_decode_boot_device common to all SoCs.
Cc: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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Allow all rockchip devices to use the hardware RNG to seed Linux
RNG.
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Reading from efuse return zero when mainline TF-A is used.
=> dump_efuse
00000000: 00 00 00 00 ....
00000004: 00 00 00 00 ....
00000008: 00 00 00 00 ....
0000000c: 00 00 00 00 ....
00000010: 00 00 00 00 ....
00000014: 00 00 00 00 ....
00000018: 00 00 00 00 ....
0000001c: 00 00 00 00 ....
However, when vendor TF-A blobs is used reading from efuse works.
Change to use auto mode, enable finish and auto access err interrupts
and set timing control using same values that vendor TF-A blob use to
fix this.
With this efuse can be read when either of mainline TF-A or vendor blob
is used.
=> dump_efuse
00000000: 52 4b 33 82 RK3.
00000004: 00 fe 21 55 ..!U
00000008: 52 4b 57 34 RKW4
0000000c: 35 30 32 39 5029
00000010: 00 00 00 00 ....
00000014: 08 25 0c 0f .%..
00000018: 02 0d 08 00 ....
0000001c: 00 00 f0 00 ....
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
Specifications:
Rockchip RK3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16/32GB memory LPDDR4x
Mali G610MC4 GPU
32GB eMMC HS400
2x USB 2.0, 2x USB 3.0
2x MIPI CSI 4x lanes
1x MIPI-DSI DPHY 2x lanes
PCIe 2.0 x1, PCIe 3.0 x4
1x HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Size: 69.6mm x 45mm (260-pin SO-DIMM connector)
Kernel commit:
2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support")
Signed-off-by: Joshua Riek <[email protected]>
Tested-by: Sam Edwards <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") added a new BROM_BOOTSOURCE_SPINOR_RK3588 with value 6.
At the time the reason for this new bootsource id value 6 was unknown.
We now know that the BootRom on RK3588 use different bootsource id
values depending on the iomux used by the flash spi controller, and not
by the type of spi nor or spi nand flash used.
Add the following enum values and use them for RK3588 boot_devices.
- BROM_BOOTSOURCE_FSPI_M0 = 3
- BROM_BOOTSOURCE_FSPI_M1 = 4
- BROM_BOOTSOURCE_FSPI_M2 = 6
Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Slawomir Stepien <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
eMMC flash (8G) included.
The device tree is taken from the kernel v6.5.
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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To make automatic Rockchip DT syncing possible from Linux to U-boot prepare
rk3288.dtsi by moving to 64 bit reg size.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Remove board_usb_init() and dm_usb_gadget_handle_interrupts() functions
related to dwc3, they use e.g. a hard-coded reg address for RK3399 and
are obsolete with use of DM_USB_GADGET.
Use of DM_USB_GADGET, USB_DWC3_GENERIC and USB_DWC3_GADGET have replaced
same feature provided by the removed functions on RK3399 boards.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).
Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 1 minutes, 14.716 seconds
After patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 2.710 seconds
Acked-by: Andrew Davis <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Reviewed-by: Nishanth Menon <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc1-v2
xilinx:
- Enable NFS, WGET, DNS and BLKMAP by default
zynqmp:
- Support new power-management node
- Remove multiple blank lines from DTSes
- Wire multiboot with DFU infrastructure
- Fix i2c-gpio pinctrl group name
- SOM DT changes (phy on kd240, kv260 cleanups
- Cleanup i2c bus on zcu1285
- DT cleanup (fix node names not to use _)
- Fix USB interrupts
- Cleanup zcu100 DT
- Add support for kaslr-seed
zynqmp_r5:
- Fix W=1 issue with missing dir
tools:
- Improve zynqmpimage mkimage support
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Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <[email protected]>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
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QEMU provides SMBIOS tables with detailed information. We should not try to
replicate them in U-Boot.
If we want to inform about U-Boot, we can add a Firmware Inventory
Information (type 45) table in future.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for J721E HS-SE 2.0 device. Make use of the existing
templates and override the phandles for sysfw.itb so that builds do not
fail.
Signed-off-by: Neha Malcom Francis <[email protected]>
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Add basic support for PHYTEC phyCORE-AM62x SoM.
Supported features:
- 2GB DDR4 RAM
- eMMC Flash
- OSPI NOR Flash
- external uSD
- Ethernet
- debug UART
Product page SoM: https://www.phytec.com/product/phycore-am62x
Device trees were taken from Linux v6.7-rc3.
Signed-off-by: Wadim Egorov <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm architecture changes:
* Move clock and pinctrl drivers out of mach-snapdragon
* Various clock driver improvements
* Convert PMIC power/reset key driver to use the button API
* Preparetory work for migrating to upstream DT
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
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With the recent changes to the Qualcomm PMIC GPIO driver the sandbox
tests for it no longer pass, update the DTS and tests to work with the
changes.
Signed-off-by: Caleb Connolly <[email protected]>
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The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Use the upstream gpio-ranges property instead of gpio-count, and drop
the bank-name property for Qualcomm boards.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.
Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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