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This avoids having to maintain to defconfigs that are 99% equivalent.
The approach is to use binman to generate two flash images,
flash-pg1.bin and flash-pg2.bin. With the help of a template dtsi, we
can avoid duplicating the common binman image definitions.
Suggested-by: Andrew Davis <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
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Update the am62 and am625 device-trees from linux v6.5-rc1. This needed
the following tweaks to the u-boot specific dtsi as well:
- Switch tick-timer to the main_timer as it's now defined in the main dtsi
- Secure proxies are defined in SoC dtsi
- Drop duplicate nodes - u-boot.dtsi is includes in r5-sk, no need for
either the definitions from main.dtsi OR duplication from u-boot.dtsi
Reviewed-by: Roger Quadros <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
Tested-by: Maxime Ripard <[email protected]>
Cc: Francesco Dolcini <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Wadim Egorov <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
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Timer0 is used by u-boot as the tick timer; Add it to the soc devices
list so it can be enabled via the k3 power controller.
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Tested-by: Maxime Ripard <[email protected]>
Tested-by: Ravi Gunasekaran <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]>
Cc: Francesco Dolcini <[email protected]>
Cc: Wadim Egorov <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
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Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
a slightly modified version of the RK3568 SoC.
Features tested on a ODROID-M1 8GB v1.0 2022-06-13:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe/AHCI
- SATA port
- USB host
Device tree is imported from linux v6.4.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
Tested-by: Stefan Agner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update config, IO and memory regions used based on [1] with pcie3x2
config reg address and reg size corrected.
Before this change:
PCI Autoconfig: Bus Memory region: [0-3eefffff],
PCI Autoconfig: Bus I/O region: [3ef00000-3effffff],
After this change:
PCI Autoconfig: Bus Memory region: [40000000-7fffffff],
PCI Autoconfig: Bus I/O region: [f0100000-f01fffff],
[1] https://lore.kernel.org/lkml/[email protected]/
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.
Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
restored to the perstn pin, a workaround to avoid having to define
a new rockchip,pins.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE
board. This board offers similar peripherals in a similar form-factor to
the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor
(which has different OPP table than the RK3399) and other minimal hardware
changes.
Kernel tag: next-20230719
Kernel commits:
- 86a0e14a82ea ("arm64: dts: rockchip: Add Radxa ROCK 4SE")
Signed-off-by: Christopher Obbard <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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To prepare for ROCK 4 SE support, changes are needed to the common ROCK
Pi 4 devicetree to move the OPP from the common devicetree to individual
board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from
Linux to gain from these changes.
Kernel tag: next-20230719
Kernel commits:
cfa12c32b96f ("arm64: dts: rockchip: correct wifi interrupt flag in Rock \
Pi 4B")
cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4")
2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+")
fd2762a62646 ("arm64: dts: rockchip: Move OPP table from ROCK Pi 4 dtsi")
Signed-off-by: Christopher Obbard <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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For RK322x series ARM SoCs the OP-TEE is non-optional, as besides the TEE
it also provides the PSCI implementation, which is expected to be available
by upstream linux.
Select CONFIG_SPL_OPTEE_IMAGE if an FIT image is built.
Signed-off-by: Alex Bee <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for
Rockchip ARM platform to indicate that an OP-TEE binary was already loaded
and a Trusted Execution Environment (TEE) is available in order to
block/reserve a memory-region for it.
This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the
OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is
selected.
That makes it a little harder to read, but I opted for that, because all
the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater
evil, IMHO. Besides it's more likley being "forgotten" to sync when changes
in u-boot-rockchip.dtsi are made.
The no longer required rockchip-optee.dtsi and it's inclusions are dropped.
The hardcoded load address is common across all OP-TEE implemenations for
Rockchip (vendor and upstream).
The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and
there will be an error if the file does not exist and/or `TEE=` build
option is missing.
Signed-off-by: Alex Bee <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Current SYS_MALLOC_F_LEN of 0x2000 (8 KB) used in SPL is too small for
some RK3568 boards. SPL will print following during boot:
alloc space exhausted
Increase the default SYS_MALLOC_F_LEN to 0x20000 (128 KB) to mitigate.
Fixes: 2a950e3ba506 ("rockchip: Add rk3568 architecture core")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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boards
Long are gone the times TF-A couldn't handle the FDT passed by U-Boot.
Specifically, since commit e7b586987c0a ("rockchip: don't crash if we
get an FDT we can't parse") in TF-A, failure to parse the FDT will use
the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two
years ago.
New boards should likely have this option disabled or explicitly enable
it in their respective defconfig.
Because existing boards might depend on a TF-A version that predates
v2.4, let's just enable this option in all RK3399 defconfigs.
Maintainers of each board can decide for themselves if they would prefer
to disable this option and allow U-Boot to pass the DT to TF-A.
Cc: Quentin Schulz <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
based on Rockchip RK3588J from Edgeble AI.
Add support for this SoM and IO board.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
based on Rockchip RK3588J from Edgeble AI.
General features:
- Rockchip RK3588J
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
- On module WiFi6/BT
Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
General features:
- microSD slot
- 1x HDMI Out
- 1x HDMI In
- 2x DP
- 1x eDP
- 2x MIPI DSI connector
- 4x MIPI CSI2 connector
- 2x USB Host
- 2x USB 3.0 OTG/Host
- 1x SATA
- 1x 2.5Gbps Ethernet
- 1x M.2 B-Key for 4G/5G cards
- 1x M.2 M-Key slot
- 1x Onboard PoE
- 1x RS485, RS232, CAN
- 1x Audio, MIC port
- RTC battery slot
- 40-pin GPIO expansion
Neu6B needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
Kernel commits:
commit <5f06c3f508f7> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6
Model B SoM")
commit <3a9181a43b94> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6
Model B IO")
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add rk3588j-u-boot.dtsi for adding U-Boot specific nodes and
properties for Rockchip RK3588J SoC.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Rockchip RK3588J is the industrial-grade version of RK3588 SoC and
is operated with -40 °C to +85 °C temparature.
Add rk3588j specific dtsi for adding rk3588j specific operating points
and other changes to be add in future.
Kernel commit:
commit <8274a04ff1dc> ("arm64: dts: rockchip: Add Rockchip RK3588J")
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add missing suffix 'A' for Edgeble Neu6A SoM and IO boards.
Fixes: <15b2d1fb727> ("board: rockchip: Add Edgeble Neural Compute
Module 6")
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
Specification:
- Rockchip RK3568
- 1/4GB LPDDR4X RAM
- 8/32GB eMMC
- SD card slot
- M.2 Connector
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125)
- HDMI 2.0
- MIPI DSI/CSI
- USB Type C 5V
The device tree is taken from kernel v6.4-rc1.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device.
Board Specifications
- Rockchip RK3568
- 2 or 4GB LPDDR4X
- 8GB or 16GB eMMC, SD card slot
- GbE LAN (Native)
- 2x 2.5G LAN (PCIe)
- M.2 Connector
- HDMI 2.0, MIPI DSI/CSI
- 2xUSB 3.0 Host
- USB Type C PD, 5V/9V/12V
- GPIO: 12-pin 0.5mm FPC connector
The device tree is taken from kernel v6.4-rc1.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
changed from DDR4 to LPDDR3.
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
This device is similar to the NanoPi R2S, and has a 16MB
SPI NOR (mx25l12805d). The reset button is changed to
directly reset the power supply, another detail is that
both network ports have independent MAC addresses.
The device tree and description are taken from kernel v6.3-rc1.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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Add support for the DSI and DSI-DPHY to U-Boot for the RGxx3. These are
needed so we can send a panel ID request to determine which panel is
being used.
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The pinctrl on the Anbernic RGxx3 for the i2c2 bus does not use the
default value, so explicitly define it.
Fixes: 6cf6fe25370c ("board: rockchip: add Anbernic RGXX3 Series Devices")
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the USB3.0 host node, and gadget node.
The gadget is available through the USB type C connector on the board.
The connector is tied to a Fairchild fusb302b device, which currently
does not have a driver in U-boot, but the node is here for correct
description of the board + Linux future compatibility.
It will be easier to move the node as-is when it will be available
in the DT from Linux
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the USB 3.0 devices in rk3588:
- USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
rk3588s
- USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
rk3588 only
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
as usbdp_phy0
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
as usbdp_phy1
- USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
mode
- associated GRFs (general register files) for the devices.
Signed-off-by: Joseph Chen <[email protected]>
[[email protected]: move nodes to right place, adapt from latest
linux kernel]
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Sync the devicetree with linux-next tag: next-20230525
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add watchdog node for the implemented mcf_wdt driver.
Signed-off-by: Angelo Dureghello <[email protected]>
---
Changes for v2:
- remove unnecessary big-endian property
Changes for v3:
- none
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Move watchdog functions inside a separate watchdog driver.
Signed-off-by: Angelo Dureghello <[email protected]>
---
Changes for v2:
- none
Changes for v3:
- none
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Remove some leftover files from the bcmcygnus platform.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Since commit 56670d6fb83f ("disk: part: use common api to lookup part
driver") part_get_info_by_name_type() ignores the part_type parameter
used to restrict the partition table type.
omap_mmc_get_part_size() and part_get_info_by_name() are the only
consumers.
omap_mmc_get_part_size() calls with part_type = PART_TYPE_EFI because at
the time of implementation a speed up could be gained by passing the
partition table type. After 5 years experience without this restriction
it looks safe to keep it that way.
part_get_info_by_name() uses PART_TYPE_ALL.
Move the logic of part_get_info_by_name_type() to part_get_info_by_name()
and replace the function in omap_mmc_get_part_size().
Fixes: 56670d6fb83f ("disk: part: use common api to lookup part driver")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This reverts commit d927d1a80843e1c3e2a3f0b8f6150790bef83da1, reversing
changes made to c07ad9520c6190070513016fdb495d4703a4a853.
These changes do not pass CI currently.
Signed-off-by: Tom Rini <[email protected]>
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Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support
Features of the sandbox FF-A support:
- Introduce an FF-A emulator
- Introduce an FF-A device driver for FF-A comms with emulated Secure World
- Provides test methods allowing to read the status of the inspected ABIs
The sandbox FF-A emulator supports only 64-bit direct messaging.
Signed-off-by: Abdellatif El Khlifi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Ilias Apalodimas <[email protected]>
Cc: Jens Wiklander <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
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add support for x0-x17 registers used by the SMC calls
In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
Results are returned in x0-x17.
This work is inspired from the following kernel commit:
arm64: smccc: Add support for SMCCCv1.2 extended input/output registers
[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=
Signed-off-by: Abdellatif El Khlifi <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Jens Wiklander <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
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- Actually merge the assorted K3 platform improvements that were
supposed to be in commit 247aa5a19115 ("Merge branch
'2023-07-21-assorted-TI-platform-updates'")
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- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU
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The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
Define the cache line size for QEMU on RISC-V to be 64 bytes.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Change the PLL clock source from syscrg to sys_syscon child node.
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Torsten Duwe <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add child node about PLL clock controller in sys_syscon node.
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Torsten Duwe <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.
This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:
+----------------+ +----------------+ <----- SPL_STACK/
| ...... | | hart 0 stack | SYS_INIT_SP_ADDR
| malloc_base | +----------------+
+----------------+ | hart 1 stack |
| GD | +----------------+ If not SMP, N=1
+----------------+ | ...... |
| hart 0 stack | +----------------+
+----------------+ ==> | hart N-1 stack|
| hart 1 stack | +----------------+
+----------------+ | ...... |
| ...... | | malloc_base |
+----------------+ +----------------+
| hart N-1 stack| | GD |
+----------------+ +----------------+
| | | |
Signed-off-by: Bo Gan <[email protected]>
Cc: Rick Chen <[email protected]>
Cc: Leo <[email protected]>
Cc: Sean Anderson <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Lukas Auer <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enabling FIT_SIGNATURE required the old authentication method to be
disabled so disable this for K3 SOCs and enable FIT_SIGNATURE for K3
Platforms.
Signed-off-by: Kamlesh Gurudasani <[email protected]>
[ cleanup the patch ]
Signed-off-by: Manorit Chawdhry <[email protected]>
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FIT signature requires the updates to u-boot.dtb and the DTB that we
pack don't get updates with the changes of the signature node.
Pack u-boot.dtb as the default DTB so that the signature node changes
can be reflected in them.
(Note, this is only packaging the primary platform and the secondary
platform will require manual changes for the FIT signature enablement)
Signed-off-by: Manorit Chawdhry <[email protected]>
[ add additional boards that were missing ]
Signed-off-by: Kamlesh Gurudasani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The 'gsub' setexpr sub command is using when creating the FIT image
configuration string on K3 devices. Enable this for K3.
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
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The background firewall calculations were wrong, fix that to determine
both the background and foreground correctly.
Fixes: 8bfce2f9989f ("arm: mach-k3: common: reorder removal of firewalls")
Signed-off-by: Manorit Chawdhry <[email protected]>
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Fix the regression that occurred during the alignment of binman series
merges along with these HS fixes that caused silent regression in this.
Fixes: 30a7ee87fd1a ("Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region")
Signed-off-by: Manorit Chawdhry <[email protected]>
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Fix regression occurred during refactoring for the mentioned commit.
Fixes: bd6a24759374 ("arm: mach-k3: security: separate out validating binary logic")
Signed-off-by: Manorit Chawdhry <[email protected]>
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Since binman is used to package bootloader images for all K3 devices, we
do not have to rely on the earlier methods to package them.
Scripts that were used to generate x509 certificate for tiboot3.bin and
generate tispl.bin, u-boot.img have been removed.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
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Move to using binman to generate tispl.bin which is used to generate the
final flash.bin bootloader for iot2050 boards.
Cc: Jan Kiszka <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
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Support added for HS-SE, HS-FS and GP boot binaries for AM62ax.
HS-SE:
* tiboot3-am62ax-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am62ax-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am62ax-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by AM62ax requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <[email protected]>
[[email protected]: changed output binary names appropriately]
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
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Support added for HS-SE, HS-FS and GP boot binaries for AM62.
HS-SE:
* tiboot3-am62x-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am62x-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am62x-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by AM62 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <[email protected]>
[[email protected]: changed output binary names appropriately]
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
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Support has been added for both HS-SE, HS-FS and GP images.
HS-SE:
* tiboot3-j721s2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j721s2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-j721s2-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by J721S2 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <[email protected]>
[[email protected]: changed output binary names appropriately]
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
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