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Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.
Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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Mark the memory node with u-boot,dm-spl so we can use it
from early SPL on both R5 and A53.
Signed-off-by: Georgi Vlaev <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size. Normally the dram_init_banksize()
setups the memory banks, while the total size is reported
by ddr_init(). This worked so far for K3 since we set the
gd->ram_size in dram_init_banksize() as well.
Signed-off-by: Georgi Vlaev <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.
Signed-off-by: Vaishnav Achath <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
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This converts the following to Kconfig:
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_KIRKWOOD_RGMII_PAD_1V8
CONFIG_KM_DISABLE_PCIE
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_FSL_PCI_VER_3_X
Signed-off-by: Tom Rini <[email protected]>
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The only mcf5445x platform does not enable PCI, drop this code.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_PCIE1
CONFIG_PCIE2
CONFIG_PCIE3
CONFIG_PCIE4
CONFIG_PCI1
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_LAYERSCAPE_NS_ACCESS
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_ESDHC_HC_BLK_ADDR
Signed-off-by: Tom Rini <[email protected]>
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As things stand currently, there is only one PowerPC platform that
enables the options for CHAIN_OF_TRUST. From the board header files,
remove a number of never-set options. Remove board specific values from
arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework
include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for
constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses
to Kconfig.
If any platforms are re-introduced with secure boot support, everything
required should still be here, but now in Kconfig, or requires migration
of an option to Kconfig.
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The way that secure boot is implemented today on NXP ARM platforms does
not reuse the elements found in include/config_fsl_chain_trust.h to
construct CONFIG_SECBOOT but instead board header files have their
environment setup as needed and then fsl_setenv_chain_of_trust() will
set secureboot in the environment. Remove a large number of unused
defines here.
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.
Cc: Peng Fan <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Kshitiz Varshney <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Make all of the CHAIN_OF_TRUST options be under a single menu and add a
comment for the rest, so the resulting config file reads more clearly.
Remove duplicate CHAIN_OF_TRUST options from
board/congatec/common/Kconfig. Remove duplicate NXP_ESBC config
questions and move to arch/Kconfig.nxp.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_KEY_REVOCATION
CONFIG_SYS_FSL_SFP_BE
CONFIG_SYS_FSL_SFP_LE
CONFIG_SYS_FSL_SFP_VER_3_0
CONFIG_SYS_FSL_SFP_VER_3_2
CONFIG_SYS_FSL_SFP_VER_3_4
CONFIG_SYS_FSL_SRK_LE
This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for
when CHAIN_OF_TRUST is enabled.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_FSL_SEC_MON
CONFIG_SYS_FSL_SEC_MON_BE
CONFIG_SYS_FSL_SEC_MON_LE
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_ESBC_HDR_LS
CONFIG_ESBC_ADDR_64BIT
Signed-off-by: Tom Rini <[email protected]>
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Now that board/freescale/common/Kconfig is safe to be included once,
globally, rename this to arch/Kconfig.nxp to better reflect that it
contains options that are valid on multiple architectures and SoC
families, and not specific to NXP reference platforms either.
Cc: Stefano Babic <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The way that we use this file currently means that we have to guard it
in every platform Kconfig. But it is also required in all NXP
platforms, including non-reference platforms. Make all options in it
have appropriate dependencies so that we can include it a single time
under arch/Kconfig
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_SYS_MAPLE
CONFIG_SYS_CPRI
CONFIG_PPC_CLUSTER_START
CONFIG_DSP_CLUSTER_START
CONFIG_SYS_CPRI_CLK
CONFIG_SYS_ULB_CLK
CONFIG_SYS_ETVPE_CLK
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
Signed-off-by: Tom Rini <[email protected]>
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We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to
Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new
symbol.
Cc: Jaehoon Chung <[email protected]>
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This converts the following to Kconfig:
CONFIG_ENABLE_36BIT_PHYS
Signed-off-by: Tom Rini <[email protected]>
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After more patches code for jumping to _start_cont symbol in flash memory
involved to code with useless mathematical operations. Currently it does:
r3 := CONFIG_SYS_MONITOR_BASE + ABS(_start_cont) - CONFIG_SYS_MONITOR_BASE
jump to r3
Which is equivalent of just:
r3 := ABS(_start_cont)
jump to r3
The purpose of that code is just to jump to _start_code symbol,
independently of program counter. So branch must be done to absolute
address. Trying to write:
ba _start_cont
just cause linker error:
LD u-boot
powerpc-linux-gnuspe-ld.bfd: arch/powerpc/cpu/mpc85xx/start.o: in function `switch_as':
(.bootpg+0x4b8): relocation truncated to fit: R_PPC_ADDR24 against symbol `_start_cont' defined in .text section in arch/powerpc/cpu/mpc85xx/start.o
make: *** [Makefile:1801: u-boot] Error 1
Probably by the fact that absolute address cannot be expressed by 24-bits.
So write the code via mtlr+blr pattern as it was before and load general
purpose register with absolute address of the symbol:
lis r3,_start_cont@h
ori r3,r3,_start_cont@l
mtlr r3
blr
Seems that gcc and gnu ld linker support symbol@h and symbol@l syntax like
number@h and number@l without any problem. And disassembling of compiler
u-boot binary proved that lis+ori instructions are called with numbers
which represent halves of absolute address of _start_cont symbol.
Signed-off-by: Pali Rohár <[email protected]>
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DT node pic@40000 is defined explicitly in p2020-post.dtsi file and also
transitionally via include file pq3-mpic.dtsi. Remove duplicate definition
from p2020-post.dtsi.
No change in final DTB file.
Signed-off-by: Pali Rohár <[email protected]>
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No functional change.
Signed-off-by: Pali Rohár <[email protected]>
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https://github.com/tienfong/uboot_mainline
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https://source.denx.de/u-boot/custodians/u-boot-amlogic
- search dtb for meson-axg-usb-ctrl on board axg
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Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add devicetrees for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel <[email protected]>
Signed-off-by: Alexandru M Stan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Devicetree headers for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2022.10 cycle:
This feature set includes mostly fixes and alignments: DT alignment with
Linux for sama7g5, removal of invalid eeprom compatibles, removal of
extra debug_uart_init calls for all at91 boards, support for pio4 driver
pioE bank, and other minor fixes and enhancements for sam9x60 and
sama5d2_icp boards.
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Versal QSPI/OSPI changes for v2022.10
- Add new flash types
- Add cadence ospi driver for Xilinx Versal
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Add support for gpio PORT E, which is available on e.g. sama7g5 SoC.
Signed-off-by: Mihai Sain <[email protected]>
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On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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When flash operated at non default mode like DDR, flash need to be reset
to operate in SDR mode to read flash ids by spi-nor framework. Reset the
flash to the default state before using the flash. This reset is handled
by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we
do raw read and write access by the registers.
Versal platform utilizes spi calibration for read delay programming, so
incase by default read delay property is set in DT. We make sure not to
use read delay from DT by overwriting read_delay with -1.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.
Signed-off-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.
This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.
This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.
Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.
With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].
Link: [1] https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a19107b8222d
Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier <[email protected]>
Tested-by: Peter Griffin <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Acked-by: Alper Nebi Yasak <[email protected]>
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In order to better compare the Linux rk3288.dtsi version
with the u-boot version move the dma-controller nodes
to the DT root.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In order to better compare the Linux rk3288.dtsi version
with the u-boot version sort the mipi,hdmi,lvds and dp nodes.
Changed:
Rename mipi_dsi label.
Rename dp nodename.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Bulk convert rk3288 DT gpios to their constant counterparts.
Partial Linux sync for the rk3288.dtsi file.
ARM: dts: rockchip: bulk convert gpios to their constant counterparts
https://lore.kernel.org/all/[email protected]/
sed -i -f script.sed rk3288.dtsi
================================
/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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With the conversion of rockchip-usb-phy.yaml a long time used fallback
string for rk3066a/rk3188 was added. The linux driver doesn't do much with
the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c
does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example
don't match. Remove the usb-phy fallback string for rk3188
to prevent possible strange side effects.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Change define condition in board_usb_init() function
to allow rk3066/rk3188 to use the USB PHY driver.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This converts the following to Kconfig:
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_MPC85XX_NO_RESETVEC
Signed-off-by: Tom Rini <[email protected]>
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Introduce board/siemens/common/Kconfig and have it hold FACTORYSET to
start with. Use select for this on the boards that need it.
Cc: Anatolij Gustschin <[email protected]>
Cc: Samuel Egli <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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