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The bootsource ids reported by BootROM of RK3528 for e.g. USB differs
compared to prior SoCs:
- Booting from USB report a new bootsource id 0x81.
Add a RK3528 specific read_brom_bootsource_id() function to help decode
this new bootsource id value to help support booting from USB on RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
SPI NOR and USB differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
Add a helper function to read the bootsource id. This helper function
will be used to translate the new values to the common BROM_BOOTSOURCE
enum values on RK3528 and RK3576.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The commit f8cb3fde935e ("arm: dts: rockchip: Fix eMMC write on RK3528")
added a missing mmc-hs200-1_8v prop to boart u-boot.dtsi.
Remove this boart u-boot.dtsi mmc-hs200-1_8v prop now that the board dt
from dts/upstream after the v6.17-dts sync includes this prop.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
SoC: RK3326
DRAM: 1 GiB (total 1022 MiB)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Use default-state prop to ensure that the blue heartbeat LED turns on
at boot to inticate that U-Boot proper has been reached.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include FDTs for all three board variants in the FIT image and adjust
the board selection code to use correct FDT in U-Boot proper.
E.g. use the odroid-go3 DT for a ODROID-GO Super device:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
DRAM: 1 GiB (total 1022 MiB)
PMIC: RK817 (on=0x80, off=0x08)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The ODROID GO2 devices come with onboard SPI flash, add support for
using the SPI flash.
The BootROM seem to expect the IDBlock at 64 KiB offset compared to the
typical 32 KiB offset from start of SPI flash used by other SoCs.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include the RK817 PMIC in SPL and enable Kconfig options to power off
the handheld gaming device when it was powered on due to a power cable
plug-in event:
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
Power Off due to plug-in event
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include pinctrl nodes and props for sdmmc, sfc and uart in SPL to ensure
pins are configured according to the device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add a new common rk3326-u-boot.dtsi and move the SoC common overrides
into it.
This should not contain any changes other than a possible reorder of
nodes and props.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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GPIO devices are needed in U-Boot proper phase, sdmmc and sfc devices
are needed in SPL and pre-reloc phase.
Update bootph- props to match what boot phase devices are needed at.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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DTs from dts/upstream already contain aliases for i2c, mmc and serial.
Remove the aliases and status=okay that are already defined in upstream
board or SoC DT.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The alias spi0 is incorrectly being re-defined in board u-boot.dtsi to
the SPI flash controller instead of the actual spi0 controller.
SPI flash support is currently not working on odroid-go2 due to missing
Kconfig options and other required device tree changes.
Remove the re-defined alias for spi0 to allow use of the real spi0,
proper SPI flash support is introduced in a later patch.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Remove the cru assigned-clocks override now that SCLK_GPU is supported
by the clock driver.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28092
- Fix a i.MX6ULL regression related to the REFTOP_VBGADJ setting.
- Shrink SPL size for the Liebherr BTT board.
- Add suppot for Toradex SMARC iMX95.
- Fix Aquila imx95 0098 Product ID.
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
A variety of Qualcomm features/fixes for this cycle, notably with a few
new platforms gaining support:
* Initial support for SDM670 (similar to SDM845), SM6350, and SM7150
platforms is added
* USB and UART issues on MSM8916 are addressed (improving stability/
reliability)
* Firmware loading is implemented for the GENI serial engine, this is
used on some platforms to load firmware for i2c/spi/uart to work
Some additional patches like binman support for building MBN files still
need some additional work.
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/8ef6ac07b35e39a57501554680bbf452e818d3e3/pipelines?ref=qcom-main
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The change in commit c1af358cf51a ("imx: mx6ull: fix REFTOP_VBGADJ
setting") is not correct. According to latest i.MX6ULL fuse table,
the REFTOP_TRIM[2:0] fuse is defined as below. So the previous codes
are correct, only need to fix the comments.
Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the
REFTOP_TRIM fuse:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Sven Schwermer reported:
"These are the symptoms: Very few of the thousands of devices that we
manufacture (< 1%) fail to decompress a large XZ archive once in Linux
userspace. We have not found any form of memory testing or other load
that reproduces this issue. Reverting the offending patch fixes this
behavior on the affected devices."
Revert the offending commit to fix the regression.
Reported-by: Sven Schwermer <[email protected]>
Signed-off-by: Ye Li <[email protected]>
[fabio: Fixed checkpatch warning and added Sven's report]
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add support for the Toradex SMARC iMX95.
Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit
Signed-off-by: João Paulo Gonçalves <[email protected]>
Co-developed-by: Emanuele Ghidoli <[email protected]>
Signed-off-by: Emanuele Ghidoli <[email protected]>
Co-developed-by: Max Krummenacher <[email protected]>
Signed-off-by: Max Krummenacher <[email protected]>
Co-developed-by: Ernest Van Hoecke <[email protected]>
Signed-off-by: Ernest Van Hoecke <[email protected]>
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Commit 2a7acc865b9d ("configs: colibri-imx8x: enable RNG support for KASLR")
enables FSL_CAAM which requires initialization in arch_misc_init().
The ARCH_MISC_INIT configuration was added to the relevant defconfig.
Commit d0ed9636902b ("global: Make ARCH_MISC_INIT a selected symbol")
changed ARCH_MISC_INIT to require explicit selection by the developer.
With this change the colibri-imx8x defconfig is no longer sufficient to
enable ARCH_MISC_INIT when FSL_CAAM is selected.
Add the necessary selection to automatically enable ARCH_MISC_INIT when
FSL_CAAM is enabled on i.MX8 platforms.
Fixes: d0ed9636902b ("global: Make ARCH_MISC_INIT a selected symbol")
Signed-off-by: Emanuele Ghidoli <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/28051
- riscv: dts: starfive: cherry-pick jh7110 updates from v6.18-rc1-dts
- riscv: Add upstream boards Milk-V Mars CM and Mars CM Lite
- timer: sifive_clint: Add GHRTv2 compaible string
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This is applied for all devices upstream in Linux now (when using the
console-specific pinctrl templates).
Signed-off-by: Stephan Gerhold <[email protected]>
Tested-by: Alexey Minnekhanov <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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There is nothing x86-centric in this include file, and moving it will
allow for some drivers to be compile-tested on sandbox.
Signed-off-by: Tom Rini <[email protected]>
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As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. This is why for all of the boards
which had an 'imply MULTI_DTB_FIT_USER_DEFINED_AREA' they then also had
to set the option in the defconfig. Drop the imply lines here.
Signed-off-by: Tom Rini <[email protected]>
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Prune overrides of upstream jh7110.dtsi now that the required nodes are
available through the devicetree-rebasing subtree.
Signed-off-by: E Shattow <[email protected]>
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Sync the kernel devicetree source files for the Allwinner SoCs with
32-bit cores that do not use OF_UPSTREAM yet. The files were taken
from a v6.18-rc1 tree.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
This commit also adds a new board devicetree for the A33 Vstar board,
plus one DT overlay for the OrangePi Zero interface board.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Andre Przywara <[email protected]>
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Sync the devicetree files from the official Linux kernel tree, v6.18-rc1.
This is covering Allwinner SoCs with 64-bit ARM cores.
The bulk is cosmetic changes: board model name changes, DT node renames,
whitespace fixes.
The actual changes are not dramatic: the CPU cores get their caches
described properly, some A64 video clocks get fixed, some A64 boards
describe the header pins for the WiFi module, the Pinephone adds an
alternative magnetometer used on some board revisions.
On the H5 side the microSD slots get marked as having no write-protect
detection, and the NanoPi Neo Plus2 board describes its regulators better.
The H6 boards switch from RSB to I2C for their PMIC connection.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <[email protected]>
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In contrast to some other Allwinner SoCs, there is no difference between
the DTs for the Allwinner A80 SoCs (sun9i) between the U-Boot and the
Linux kernel repository.
Remove the old copies of the A80 related .dts and .dtsi files, and switch
most of sun9i boards over to use OF_UPSTREAM.
There is the Sunchip CX-A99 (family of) board(s) for which we don't have
a DT in the kernel tree. Keep the .dts file in the legacy U-Boot DT
directory, and let the board's defconfig opt out of OF_UPSTREAM.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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In contrast to some other Allwinner SoCs, there is no difference between
the DTs for the Allwinner T113-s3 SoC (sun20i) between the U-Boot and the
Linux kernel repository.
Remove the old copies of the T113-s3 related .dts and .dtsi files, and
switch the whole SoC (represented by just one board) over to use
OF_UPSTREAM.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The H6 and H616 DRAM initialisation code recently gained a joint and
improved size detection routine, which helped to avoid the occasional
DRAM size misdetection.
Use the same code for the A523 DRAM initialisation as well, which
suffers from the same misdetection at times.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
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The idiom used in save_boot_params is common for armv7.
In armv8 is much easier to do the same thing with adr/adrp.
So let's simplify the code a bit.
Signed-off-by: Ilias Apalodimas <[email protected]>
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With the memory map configuration being done dynamically, reserve extra
space during U-Boot relocation to ensure we have enough for the fixups.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
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K3 platforms have reserved memory regions for TFA and OPTEE which should
be unmapped for U-Boot. While other "no-map" memory regions like the
memory pools for remote cores should not be unmapped to allow U-Boot to
load firmware during remoteproc.
Therefore this patch adds the necessary fdt fixups to properly set the
load address for TFA/OPTEE and unmaps both by mmu_unmap_reserved_mem.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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The boot flow in K3 platforms requires the subsequent boot stages to be
aware of the memory reserved for previous boot binaries. In the regular
boot sequence of:
R5 SPL -> ATF -> OP-TEE -> A-core SPL -> U-Boot -> Kernel,
Both A-core SPL and U-Boot should be made aware of the memory reserved
for ATF and OP-TEE from their device-tree. Currently this information is
absent.
Therefore this patch adds the reserved-memory regions as part of
spl_perform_arch_fixups for the next stage's DT. This is called during
both R5 and A-core SPL which fixes up the DT for their respective next
stages: A-core SPL and U-Boot proper.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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The current spl_board_fixups API allows for modification of spl_image
before the SPL jumps to it. This can be used to modify the DT for the
next boot stage, however the current API only allows either the machine
arch or the board to use it.
This limits the utility of the API as there might be certain fixups that
should be applied to all boards sharing the same machine architecture
with others being board specific.
For TI's K3 specifically, this prevents us from performing architecture
level fixups since a lot of TI boards are already making use of the
spl_board_fixups API.
Therefore this patch splits the API into two to allow both board and the
architecture specific fixups. The order is kept as arch then board to
give board specific fixups the precedence.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU's page tables, done by mmu_setup.
Though this works well for simpler platforms, it makes creating runtime
carveouts by modifying the static array at runtime exceedingly complex
like in mach-snapdragon/board.c.
Creation of such carveouts are much better handled by APIs such as
mmu_change_region_attr once the page tables are configured. Usually such
carveouts are configured via the device-tree's reserved-memory node
which provides the address and size for the carveout.
Therefore this patch adds mmu_unmap_reserved_mem which acts as a wrapper
over mmu_change_region_attr, helping unmap a reserved-memory region.
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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The static memory map for K3 (k3_mem_map) only maps the first DRAM bank
and therefore doesn't scale for platforms with multiple memory banks.
This patch modifies enable_caches to add mem_map_from_dram_banks which
appends all the memory banks to k3_mem_map before calling mmu_setup.
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU as part of mmu_setup.
But since the exact configuration of memory banks might not be known at
build time, many platforms such as imx9, versal2 etc. utilize
gd->bd->bi_dram to configure the static map at runtime.
Therefore this patch adds a new API mem_map_from_dram_banks that
modifies the static map in a similar way. Allowing the caller to map all
dram banks by just passing the index to last entry in their mem_map and
it's length.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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In dcache_enable, currently the dcache entries are only invalidated when
the MMU is not enabled. This causes issues when dcache_enable is called
with the MMU already configured, in such cases the existing dcache
entries are not flushed which might result in un-expected behavior.
This patch invalidates the cache entries on every call of dcache_enable
before enabling dcache (by setting CR_C). This makes dcache_enable
behave similar to icache_enable as well.
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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The mmu_setup function configures the page tables based on the board
supplied mem_map struct array. It is called implicitly as part of
dcache_enable but this limits us to only be able to use APIs such as
mmu_change_region_attr only after caches are enabled.
This might lead to speculative accesses before we can unmap a region
that is marked as cacheable in the static memory map.
Therefore this patch exports the mmu_setup function in mmu.h allowing
users to have more control over when the mmu is configured.
For K3 specifically this allows for the following configuration sequence
as part of enable_caches:
static mem_map fixups (TODO) -> mmu_setup -> carveouts using
mmu_change_region_attr (TODO) -> icache/dcache enable
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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U-Boot's provided enable_caches enforces the following sequence:
icache_enable -> mmu_setup (as part of dcache_enable) -> dcache_enable
Whereas for K3 devices, we would like to add entries to the provided
static array (k3_mem_map) as per gd->bd->bi_dram and then call mmu_setup
to configure the MMU but also create carveouts for TFA/TEE before we
enable caches to prevent speculative accesses to the region. Thus the
following desired sequence:
add dram banks -> mmu_setup -> carveout TFA/TEE -> icache/dcache enable
Therefore this patch adds K3's own implementation of enable_cache for
ARM64, allowing for greater control over the cache enablement sequence.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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The K3 family of SoCs encompasses a wide variety of devices with varying
DDR configurations and memory carveout requirements, the current static
memory map provides basic support for TI EVMs but does not scale well
for newer platforms (such as AM62SiP with 512MiB of RAM).
Therefore this patch replaces the existing memory map with a minimal
one, that could be more easily modified at runtime.
Reviewed-by: Dhruva Gole <[email protected]>
Signed-off-by: Anshul Dalal <[email protected]>
Tested-by: Wadim Egorov <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2026.01 cycle:
This small fixes set includes a change on clocks register value and a
fix for the sam9x60ek default timer.
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This reverts commit a040578d8270ed8788d7663808ea63ce5ffd7840.
Based on feedback other SOCs (for example Star64) are using driver in non
DMA mode which is causing issues that's why revert this patch.
cdns,is-dma should be removed differently.
Signed-off-by: Michal Simek <[email protected]>
Reported-by: E Shattow <[email protected]>
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As requirement of CR side, QSPI Flash usage via RPC driver shall
be disabled and leaving the control of this module to CR side.
Perform DT modification to disable the RPC SPI.
Signed-off-by: Nguyen Tran <[email protected]>
Reviewed-by: Khanh Le <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
[Marek: Do not modify defconfig, modify the DT instead, this way
the RPC SPI can be enabled without recompiling the U-Boot
itself. Update commit message accordingly.]
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Commit 63da3a795e86 ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts")
removed unnecessary V4H DTs from arch/arm/dts , but in the process
also incorrectly dropped the -u-boot.dtsi U-Boot extras. Reinstate
those extras.
Due to DT file name change for the R8A779H0 V4M Gray Hawk, update
the r8a779h0-gray-hawk-u-boot.dtsi filename to newly matching
r8a779h0-gray-hawk-single-u-boot.dtsi .
Align r8a779h0-u-boot.dtsi with clean up commits
1487c34efa7b ("arm64: dts: renesas: Deduplicate extalr_clk bootph-all")
dd8f57ed2f0b ("ARM: dts: renesas: Drop most of bootph-* tags")
Fixes: 63da3a795e86 ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts")
Signed-off-by: Marek Vasut <[email protected]>
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Commit 3faeb78378ea ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node")
incorrectly re-enabled the RPC SPI DT node, which was disabled in commit
13bdb6a26910 ("ARM: dts: renesas: Disable RPC driver on R8A779G0 V4H White Hawk board")
Reinstate the disablement.
Fixes: 3faeb78378ea ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node")
Signed-off-by: Marek Vasut <[email protected]>
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U-Boot currently enables the UPLL during boot, which triggers a udelay()
call that depends on the system tick timer. Since no explicit tick source
is defined in the device tree, boot stalls on this board.
Define the "tick-timer" property under /chosen and point it to the PIT
node, ensuring U-Boot uses the PIT as the tick source.
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Dharma Balasubiramani <[email protected]>
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This reverts commit a681cfecb4346107212f377e2075f6eb1bdc6a2b.
It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.
Reported-by: E Shattow <[email protected]>
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Yao Zi <[email protected]>
Acked-by: E Shattow <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Partly revert commit 726404a66c773 ("airoha: rework RAM size handling
to support multiple RAM size").
The general idea is good, but the call of
get_ram_size((void *)gd->ram_base, SZ_8G);
produces the following result on my an7581 board with only 1Gb of
memory:
"Synchronous Abort" handler, esr 0x96000004
elr: 0000000081e201c8 lr : 0000000081e20160 (reloc)
elr: 00000000bff501c8 lr : 00000000bff50160
x0 : 0000000180000000 x1 : 0000000100000000
x2 : 000000000000002e x3 : 0000000000000002
x4 : 000000001fbf0000 x5 : 0060000000000401
x6 : 0000000000000000 x7 : 00000000bffdb268
x8 : 0000000000000060 x9 : 00000000bffdb2c8
x10: 0000000000000000 x11: 0000000000000060
x12: 00000000bffdb268 x13: 00000000841c56d0
x14: 00000000841c56d0 x15: 0000000000000000
x16: 00000000841506e4 x17: dd7fe29aec3b07e8
x18: 00000000bf710e00 x19: 0000000080000000
x20: 0000000000000000 x21: 0000000020000000
x22: 0000000200000000 x23: 0000000000000001
x24: 0000000040000000 x25: 00000000bf708e78
x26: 00000000bf7bdca0 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000bf708e20
Code: 910943ff d65f03c0 d37df2a1 8b150e60 (f8616a62)
Resetting CPU ...
So just not call get_ram_size() and use the value from dtb.
Fixes: 726404a66c773 ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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