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The host-index-min property is invalid,
so it inherits from the sdmmc definition in dtsi.
Signed-off-by: Xiaobo Tian <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Correct the LEDS label name and remove the board type prefix,
which is actually unnecessary here, removes the redefined system status LED pin.
Signed-off-by: Xiaobo Tian <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-u-boot.dtsi file.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. This file has recently had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Problem: board_spl_was_booted_from return wrong boot_devices[3] value
/spi@ff1d0000 and same-as-spl dont work properly for SPINOR flash
because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device
need parse SPINOR flash node as UCLASS_SPI_FLASH
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d0000 > board_boot_order: could not map node @618 to a boot-device
/sdhci@fe330000 > /mmc@fe320000
Solution: just change it to /spi@ff1d0000/flash@0
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d0000/flash@0 > /sdhci@fe330000 > /mmc@fe320000
Signed-off-by: Artem Lapkin <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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If ddr3_init() fails then DDR was not initialized and we cannot load and
execute U-Boot. We cannot continue, we cannot do anything in this case, so
hang.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files
to correct SOC/platform value. So do not overwrite it in board config
include files.
Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses
200 MHz TCLK.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove
useless default CONFIG_SYS_TCLK value from the end of soc.h file.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20210809
- new SOC: add support for imx8ulp
- Toradex fixes for colibri (vf / imx6 / imx7 / imx8x)
- convert to DM for mx28evk
- Fixes for Gateworks ventana boards
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
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cmd_tbl_t is removed, need use struct cmd_tbl
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART
Log as below: I would keep some debug info for now, and after we move
to be stable and production launch, we could drop that.
U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
Normal Boot
upower_init: soc_id=48
upower_init: version:11.11.6
upower_init: start uPower RAM service
user_upwr_rdy_callb: soc=b
user_upwr_rdy_callb: RAM version:12.6
Turn on switches ok
Turn on memories ok
Clear DDR retention ok
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F0 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
complete
De-Skew PLL is locked and ready
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x3a800 by ROM_API
NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94
NOTICE: BL31: Built : 01:56:58, Jun 29 2021
NOTICE: upower_init: start uPower RAM service
NOTICE: user_upwr_rdy_callb: soc=b
NOTICE: user_upwr_rdy_callb: RAM version:12.6
U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
CPU: Freescale i.MX8ULP rev1.0 at 744 MHz
Reset cause: POR
Boot mode: Single boot
Model: FSL i.MX8ULP EVK
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... ***
Warning - bad CRC, using default environment
In: serial@293a0000
Out: serial@293a0000
Err: serial@293a0000
Net:
Warning: ethernet@29950000 (eth0) using random MAC address -
96:35:88:62:e0:44
eth0: ethernet@29950000
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8ULP dtsi
Signed-off-by: Peng Fan <[email protected]>
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Add upower api support, this is modified from upower firmware exported
package.
Signed-off-by: Peng Fan <[email protected]>
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Move struct mu_type to common header to make it reusable by upower and
S400
Signed-off-by: Peng Fan <[email protected]>
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When booting from boot part1/2, the image offset should be 0, but
ROM has a bug to return 0x8000. Has to workaround the issue before
ROM fix it.
Use a ROM function to know boot from emmc boot part or user part
So we can set the image offset accordingly.
Signed-off-by: Ye Li <[email protected]>
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Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian,
it does not connect to low 16 bits for RTD. So we can't get the correct
boot mode.
Change to use DGO_GP5 of SEC_SIM which is set by ROM.
Signed-off-by: Ye Li <[email protected]>
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The CMC1 SRS reflects the current reset cause, not SSRS.
Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8ULP iomuxc support
Signed-off-by: Peng Fan <[email protected]>
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Add imx_get_mac_from_fuse for enet build pass
Signed-off-by: Peng Fan <[email protected]>
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Configure DCNANO and MIPI_DSI to be controlled by AD for single boot
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Read from ROM API to get current boot device.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Need probe the S400 MU device in arch_cpu_init_dm, so we can use
S400 API in u-boot
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Unify rdc function to rdc.c
Update soc.c to use new rdc function
Signed-off-by: Peng Fan <[email protected]>
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Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
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Add TRDC release request, then we could configure resources to be
accessible by A35 Domain.
Signed-off-by: Peng Fan <[email protected]>
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There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.
Signed-off-by: Peng Fan <[email protected]>
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Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add API to support fuse read and write
Signed-off-by: Ye Li <[email protected]>
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The RDC API is updated to add a field for XRDC or TRDC
Signed-off-by: Ye Li <[email protected]>
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Add S400 API for image authentication
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Disable wdog3 which is configured by ROM
Signed-off-by: Peng Fan <[email protected]>
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SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li <[email protected]>
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Add i.MX8ULP clock support
Signed-off-by: Peng Fan <[email protected]>
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Add MU driver and S400 API. Need enable MISC driver to work
Signed-off-by: Ye Li <[email protected]>
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Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig
public to both.
Signed-off-by: Peng Fan <[email protected]>
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i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure
for i.MX8ULP
Signed-off-by: Peng Fan <[email protected]>
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Since the container is shared among i.MX platforms, move its header file
to mach-imx
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Since we will re-use the container parser on imx8ulp, move the codes
to mach-imx
Signed-off-by: Ye Li <[email protected]>
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Add basic i.MX8ULP support
For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add get reset cause function to show what triggerred reset.
Signed-off-by: Peng Fan <[email protected]>
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Support print cpu info. the clock function has not been added, it will
be added in following patches.
Signed-off-by: Peng Fan <[email protected]>
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These defines could be reused by i.MX8ULP, so move them
to common header.
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8ULP cpu type and helpers.
Signed-off-by: Peng Fan <[email protected]>
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