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Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")
Signed-off-by: Peng Fan <[email protected]>
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Add type of set_clk_eqos to make it could be used by other files.
Signed-off-by: Peng Fan <[email protected]>
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Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")
Signed-off-by: Peng Fan <[email protected]>
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use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK board, we will use
CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK board.
Signed-off-by: Peng Fan <[email protected]>
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Add board code to configure the network interface
Add net defconfig
Signed-off-by: Peng Fan <[email protected]>
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The dm root node is needed early in the spl to allow the timer to be
used. This change calls spl_early_init to initialize the dm root node.
Signed-off-by: Greg Gallagher <[email protected]>
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Giant board is a tiny SBC based on the Adafruit Feather form factor,
created by groboards it contains a SAMA5D2 processor (SAMA5D27),
128 MB of RAM and a microSD card for storage.
Signed-off-by: Greg Gallagher <[email protected]>
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Because ATMEL_BASE_ROM is defined to 0x100000, it already points
to the begin of the index table for 512 byte sectors correction.
Thus its offset must be zero and the index of the table for 1024
byte sectors must start at offset 0x8000.
Signed-off-by: Kai Stuhlemmer (ebee Engineering) <[email protected]>
[ta: update commit message]
Signed-off-by: Tudor Ambarus <[email protected]>
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Offsets are described in the datasheet at section:
"11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction".
For testing I "injected" bit flips into u-boot NAND memory area,
and then read back. PMECC could not correct the errors. With the
offsets updated everything is fine.
Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support")
Signed-off-by: Tudor Ambarus <[email protected]>
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Implement drive strength support, by preserving the same bindings
as in Linux.
Signed-off-by: Eugen Hristev <[email protected]>
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This adds support for the NanoPi R2S from FriendlyArm.
Rockchip RK3328 SoC
1GB DDR4 RAM
Gigabit Ethernet (WAN)
Gigabit Ethernet (USB3) (LAN)
USB 2.0 Host Port
MicroSD slot
Reset button
WAN - LAN - SYS LED
Signed-off-by: David Bauer <[email protected]>
Reviewed-by: Kever Yang<[email protected]>
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The rng is embedded in the SoC so enable it in the device tree
universally, the use of it can be controlled by enabling/disabling
at the device config level.
Signed-off-by: Peter Robinson <[email protected]>
Cc: Kever Yang <[email protected]>
Reviewed-by: Kever Yang<[email protected]>
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Add missing regulator-init-microvolt property to vdd_log regulator.
Signed-off-by: Kever Yang <[email protected]>
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Add missing regulator-init-microvolt property to vdd_log regulator.
Signed-off-by: Kever Yang <[email protected]>
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Add missing regulator-init-microvolt property to vdd_center regulator.
Signed-off-by: Kever Yang <[email protected]>
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SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0. Formerly the alias spi1
pointed to &spi5, use an alias spi5 for this instead.
Signed-off-by: Hugh Cole-Baker <[email protected]>
Suggested-by: Kever Yang <[email protected]>
Reviewed-by: Kever Yang<[email protected]>
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SPI flash on this board is located on bus 1, default to using bus 1 for
SPI flash on both rk3399-roc-pc and -mezzanine, and stop aliasing it to
bus 0.
Signed-off-by: Hugh Cole-Baker <[email protected]>
Suggested-by: Simon Glass <[email protected]>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<[email protected]>
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The input system clock for mt7622 timer is 10MHz and can be retrieved
through the clk driver.
Signed-off-by: Weijie Gao <[email protected]>
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Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.
However, currently the patch supports only the booting from
memory-mapped SPI flash.
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.
AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.
A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
Signed-off-by: Dylan Hung <[email protected]>
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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This patch adds the clock control driver
for the AST2600 SoC.
Signed-off-by: Ryan Chen <[email protected]>
Signed-off-by: Chia-Wei, Wang <[email protected]>
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Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h
Signed-off-by: Kate Liu <[email protected]>
Signed-off-by: Alex Nemirovsky <[email protected]>
CC: Tom Rini <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h by proxy. This file does not exist for the ARM
architecture and thus code compilation failed when using this
driver on ARM.
Signed-off-by: Harm Berntsen <[email protected]>
CC: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
QEMU.
Signed-off-by: Harm Berntsen <[email protected]>
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Enable the USB port for MT8516 Pumpkin Board.
Signed-off-by: Fabien Parent <[email protected]>
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Add support for USB on mt8516 based SoC.
Signed-off-by: Fabien Parent <[email protected]>
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- R-Car pinctrl updates
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- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
- Select TIMER_EARLY to avoid infinite recursion for Trace.
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Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"
Signed-off-by: Lad Prabhakar <[email protected]>
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Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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If no need cache support, not build the cache files, such as in SPL.
Signed-off-by: Peng Fan <[email protected]>
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In order to remove the arch-specific ifdefs around initr_trap, introduce
arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have
been moved to arch/<arch>/lib/traps.c
Default implementation is a nop stub.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Add a return value to noncached_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add a return value to cpu_secondary_init_r and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add test for dropped trace before log_init, displayed by debug uart.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Enable BINMAN when using Arm-Trusted-Firmware (ATF) to
generate FIT images.
Signed-off-by: Siew Chin Lim <[email protected]>
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Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim <[email protected]>
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SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang <[email protected]>
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mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang <[email protected]>
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In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang <[email protected]>
Signed-off-by: Siew Chin Lim <[email protected]>
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These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).
Signed-off-by: Siew Chin Lim <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang <[email protected]>
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Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang <[email protected]>
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Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang <[email protected]>
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Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
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