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Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Update the list of defconfigs, this was missed with the last pull
request of the u-boot-riscv tree.
Signed-off-by: Tom Rini <[email protected]>
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Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.
Moving the DTB in front of the kernel can avoid this error.
Signed-off-by: Randolph <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350"
Signed-off-by: Randolph <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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