| Age | Commit message (Collapse) | Author |
|---|
|
Some versions of KVM don't allow access to the cycle CSR.
Provide a command 'exception rdcycle' for testing.
If the cycle CSR is accessible, we get an output like:
=> exception rdcycle
cycle = 0x41f7563de
If the cycle CSR is not accessible, we get an output like:
=> exception rdcycle
Unhandled exception: Illegal instruction
Put subcommands into alphabetical order in long help.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
After adding the U_BOOT_LONGHELP macro some new commands came in still
that were not making use if it. Switch these cases over and in a few
places add missing newlines as well.
Signed-off-by: Tom Rini <[email protected]>
|
|
The common.h should not be used anymore.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
A 16 bit aligned instruction should generated an exception if the C
extension is not available.
Provide an 'extension ialign16' command for testing exception handling.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception ialign16
Unhandled exception: Instruction address misaligned
EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
Eliminating the C extension on application processors is under
discussion.
Support emitting a compressed instruction. This will lead to an
illegal instruction exception if the C extension is not implemented.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception compressed
Unhandled exception: Illegal instruction
EPC: 0000000087731708 RA: 000000008773fe44 TVAL: 0000000000004501
EPC: 000000008001b708 RA: 0000000080029e44 reloc adjusted
Code: 0b93 0000 0493 0000 0993 0000 f06f ccdf (4501)
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
The ebreak instruction should generate a breakpoint exception.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
The command 'exception' can be used to test the handling of exceptions.
Currently the exception command only allows to create an illegal
instruction exception on RISC-V.
Provide a sub-command 'exception unaligned' to cause a misaligned load
address exception.
Adjust the online help for 'exception undefined'.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <[email protected]>
|
|
The 'exception' command allows to test exception handling.
This implementation supports ARM, x86, RISC-V and the following exceptions:
* 'breakpoint' - prefetch abort exception (ARM 32bit only)
* 'unaligned' - data abort exception (ARM only)
* 'undefined' - undefined instruction exception
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
