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Enable CONFIG_DFU_MTD and CONFIG_DM_MTD to support DFU transfers
over MTD partitions, required for FWU multi-bank update using
NOR flash.
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Resync all defconfig files using qconfig.py
Signed-off-by: Tom Rini <[email protected]>
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GPIO delay driver is necessary to use to extend delay times for USB hubs.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6744d3a93f48658178a53d218a4a6ca2fbb050dd.1771325431.git.michal.simek@amd.com
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Enabled the default utilization of the NFS command on all Xilinx
platforms to facilitate booting images through the network using
the NFS protocol.
Signed-off-by: Pranav Tilak <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Enable the new PCA9541 i2c bus arbiter on AMD/Xilinx SOCs by default.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/edfb7e7a6e800484d3ac3bf45a4f83adfcdd1754.1764170621.git.michal.simek@amd.com
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Enable SNTP/DATE commands on all Xilinx boards.
Also enable RTC_EMULATION driver for platforms which don't have physical
RTC. Enabling DM_RTC is enabling by default also CMD_DATE.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2605b1618a311efe4f35442c34e7cec973060630.1759393175.git.michal.simek@amd.com
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Enable MSCC phy driver instead of VITESSE. Vitesse driver is much older and
is on the way out that's why switch to MSCC driver which covers VSC8531
which is used on one Versal board.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/0a441e488a29bd1c93677a6f63a4a04a3cc1c9f5.1759216164.git.michal.simek@amd.com
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The most of OFFSET values are in hex instead of int which is easier for
layout description.
Signed-off-by: Michal Simek <[email protected]>
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Driver fully depends on firmware driver to be present that's why change
imply to depends on to cover it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/bd18a4ce3e65411bb956636d4a2ef4b5fbe8b9e1.1749104235.git.michal.simek@amd.com
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Marek Vasut <[email protected]> says:
Rename the environment related variables and add ENV_ prefix, so that
all configuration options which are related to environment would have
an CONFIG_ENV_ prefix. No functional change.
Link: https://lore.kernel.org/r/[email protected]
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Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Resync all defconfig files using qconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Remove uartlite serial driver from defconfigs because is not tested or used
on ARM based platform as console.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/86b100692101089dd8d9a8eed45461e8855384bc.1744270698.git.michal.simek@amd.com
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The zynqmp gem driver support max MTU size 1536, so remove tftp
block size 4096 from defconfig and use default tftp block size.
Fixes: a33b4b96b3cf ("xilinx: Enable MBEDTLS/LWIP/WGET and WGET_HTTPS")
Signed-off-by: Padmarao Begari <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Enable lwip and https on our platforms to be able to use it in a boot.
Acked-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/cb05adaf0758c2c4f1361f8665169897493638e7.1738164681.git.michal.simek@amd.com
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Enable meminfo command to be able to see where things are mapped.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/b7f9f5e18e16a945277d4b8cfde5a7f057e77676.1737976295.git.michal.simek@amd.com
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Build mkfwumdata tool by default for building ab mdata structure.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6d82c9a2db30e12ea17fa125c68a555d7f070851.1737723845.git.michal.simek@amd.com
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Added support for Infineon Octal flash components on the
Versal and Versal Net platforms.
Signed-off-by: Tejas Bhumkar <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Enable automatic dfu_alt_info variable generation based on MTD partition.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/67ff88c8c7186138353c0b74ed37a318fb4b199e.1733395093.git.michal.simek@amd.com
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc3:
- microblaze:
- Disable JFFS2
- fpga:
- pass compatible flag to fpga_load()
- zynqmp:
- SOM RTC fix
- SC(system controller) PMW polarity fix
- Fix ram_top calculation with introducing XILINX_MINI
- Fix RPU release command
- versal:
- Enable capsule update
- Enable soft reset and Micron octal flashes
- xilinx:
- Align Kconfig regarding SPI_STACKED_PARALLEL
- bootcount:
- Add new zynqmp driver
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Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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The Micron MT35 series octal flashes can be activated
through the configuration option CONFIG_SPI_FLASH_MT35XU.
To ensure their detection, enable this option in the
default defconfig for octal flashes.
Signed-off-by: Tejas Bhumkar <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Enable capsule update in SD boot mode. For getting it work there is a need
to generate or setup dfu_alt_info and enable sysreset with DFU_MMC.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/cede513de764b99560dc3737457dbc8a5cc71d21.1729857366.git.michal.simek@amd.com
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Align defconfigs with the latest Kconfig layout.
Fixes: f896aa656774 ("mtd: spi-nor: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL")
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/fe05a0e542d6117c10956e4a104123e46f956793.1730450241.git.michal.simek@amd.com
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Venkatesh Yadav Abbarapu <[email protected]> says:
This series adds support for Xilinx qspi parallel and
stacked memeories.
In parallel mode, the current implementation assumes that a maximum
of two flashes are connected. The QSPI controller splits the data
evenly between both the flashes so, both the flashes that are connected
in parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can differ
in sizes. So, except the sizes all other flash parameters of both the flashes
are identical.
Spi-nor will pass on the appropriate flash select flag to low level driver,
and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where addr
is the address specified by the user.
Similarly for read and erase operations it will read from both flashes, so
size and offset are divided by 2 and send to flash.
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Enable the SPI_ADVANCE config option for all xilinx platforms, as
this is required for parallel-memories.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Enable simple-pm-bus driver to handle case where axi bus coming between PS
(fixed) part to PL (programmable) part has own clock or power domain.
That's why enable driver to be ready for this configuration.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/b9f4bb85be502616edf3be2b79e52a0e2c03e821.1725349691.git.michal.simek@amd.com
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Enable setting speed mode using mmc dev commands.
The speed mode is provided as the last argument in these commands
(ex: mmc dev 0 0 10) and is indicated using the index from enum
bus_mode in include/mmc.h. A speed mode can be set if it is enabled
from device tree or from capabilities register
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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It is good to be aware what information is shared via smbios interface
that's why enable it by default.
Signed-off-by: Michal Simek <[email protected]>
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Enable FFA_TRANSPORT which also enable FFA command.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5a850b1558fad0f05c61de82110abe4c0e7fd2e4.1718104009.git.michal.simek@amd.com
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Boards which have for example MAC address in eeprom but not in Xilinx
format (legacy or FRU) could reference it via nvmem cells.
For example:
&gem0 {
nvmem-cells = <&mac>;
nvmem-cell-names = "mac-address";
};
&eeprom {
#address-cells = <1>;
#size-cells = <1>;
mac: mac-address@f0 {
reg = <0xf0 6>;
};
};
For getting it work above DT changes are required but also CONFIG_NVMEM
should be enabled. That's why enable it by default in generic defconfigs
to be able to use it directly by changing DT only.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/9c8ee7a4c7a16367438a92a4c9581bac9d968f84.1712815454.git.michal.simek@amd.com
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Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.
Signed-off-by: Marek Vasut <[email protected]>
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com
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Enabled the default utilization of the NFS command across all Xilinx
platforms to facilitate the booting of images through the network
using the NFS protocol.
Fixes: 10de12570799 ("disable NFS support by default")
Signed-off-by: Tejas Bhumkar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Enable DNS/WGET and BLKMAP to be able to download images over HTTP and map
them.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/4fa9b425459947e6424c8ce27376fdc7a14bf839.1696592702.git.michal.simek@amd.com
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Align default SPI configuration with ZynqMP/Versal NET.
There is no reason to run on lower frequencies.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c1d6ebd659f3002649b1200c926f8b9ed3132085.1698749448.git.michal.simek@amd.com
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Kernel Address Space Layout Randomization (KASLR) is a hardening
feature that aims to make it more difficult to take advantage
of known exploits in the kernel, by placing kernel data structures
at a random address at each boot.The bootloader supports randomizing
the virtual address at which the kernel image is loaded.
The bootloader must provide entropy by passing a random u64 value
in the /chosen/kaslr-seed device tree node.
When we run "kaslrseed" command from U-Boot, the bootloader will
genarate the kaslr-seed and update the /chosen/kaslr-seed DT property.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Enable it for TPM usage.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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TPMs are becoming popular that's why enable drivers
and command for it.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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HBM stands for high bandwidth memory and is a type of memory interface used
in 3D-stacked DRAM (dynamic random access memory) in some AMD GPUs (aka
graphics cards), as well as the server, high-performance computing (HPC)
and networking and client space. High Bandwidth Memory(HBM) has total 16
channels, one channel is divided into two pseudo channels which makes its
32 banks each with some amount of memory.
And then we have DDR_LOW PS low, DDR_HIGH0 PS high, DDR_HIGH1 PS very high
and pretty much there should be also place for PL DDR. So maximum number of
memory banks will be 36, updating the CONFIG_NR_DRAM_BANKS to 36.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ed9eaf5c20501ee691d7d28a173511cd9a87f161.1690958095.git.michal.simek@amd.com
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Versal VEK280 board has Analog Devices ethernet phy. So, enable
CONFIG_PHY_ADIN config in Versal defconfig.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Qemu can create virtio mmio transports and passing devices through it
that's why enable virtio by default on all arm64 based SoCs.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/a2ee18e7e8c1881ce72c5cd13127794a02410696.1679583129.git.michal.simek@amd.com
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