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Signed-off-by: Peter Tyser <[email protected]>
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There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala <[email protected]>
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By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.
Signed-off-by: Kumar Gala <[email protected]>
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Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE. Also reworked it to use one line per file
for everything and sorted in alphabetical order.
Signed-off-by: Kumar Gala <[email protected]>
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P1011 - Single core variant of P1020
P2010 - Single core variant of P2020
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Travis Wheatley <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We
also have SERDES init code for the 8536.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Dejan Minic <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
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All 85xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers. (83xx, 85xx, 86xx).
The code is broken up into the following steps:
GET_SPD
COMPUTE_DIMM_PARMS
COMPUTE_COMMON_PARMS
GATHER_OPTS
ASSIGN_ADDRESSES
COMPUTE_REGS
PROGRAM_REGS
This allows us to share more code an easily allow for board specific code
overrides.
Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Ed Swarthout <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.
Added support for using the ePAPR defined spin-table mechanism on 85xx.
Signed-off-by: Kumar Gala <[email protected]>
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Add a set of functions to manipulate TLB entries:
* set_tlb() - write a tlb entry
* invalidate_tlb() - invalidate a tlb array
* disable_tlb() - disable a variable size tlb entry
* init_tlbs() - setup initial tlbs based on static table
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
And removed hard i2c path from a few u-boot.lds scipts too.
Minor whitespace cleanups along the way.
Signed-off-by: Jon Loeliger <[email protected]>
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Based on patch by Mike Frysinger, 20 Jun 2006
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Modifications are based on the linux kernel approach and
support two use cases:
1) Add O= to the make command line
'make O=/tmp/build all'
2) Set environement variable BUILD_DIR to point to the desired location
'export BUILD_DIR=/tmp/build'
'make'
The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'
Command line 'O=' setting overrides BUILD_DIR environent variable.
When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
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Move the TSEC driver out of cpu/mpc85xx as it will be shared
by the upcoming mpc83xx family as well.
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- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Minor code cleanup
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