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Signed-off-by: Peter Tyser <[email protected]>
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The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.
Signed-off-by: Kumar Gala <[email protected]>
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On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala <[email protected]>
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There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility. Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if
we are e500 v2 would miss future parts (like e500mc).
Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.
Signed-off-by: Kumar Gala <[email protected]>
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While in probecpu() UART is still not initialized.
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.
Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The number of CPUs are getting detected dynamically by checking the
processor SVR value. Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.
This can help to use the same u-boot image across the platforms.
Also revamped and corrected few Freescale Copyright messages.
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC
Signed-off-by: Peter Tyser <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:
85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register. These bits
only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
status register. We may as well clear all 32 bits of the register...
86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
the controller
- Clear the channel start bit in the DMA mode register after a transfer
Signed-off-by: Peter Tyser <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication
Signed-off-by: Peter Tyser <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Haiying Wang <[email protected]>
Acked-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Andy Fleming <[email protected]>
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Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Travis Wheatley <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Only print 4 cpu freq per line. This way when we have 8 cores its a
bit more readable.
Signed-off-by: Kumar Gala <[email protected]>
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This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
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Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <[email protected]>
Acked-by: Kumar Gala <[email protected]>
Acked-by: Jon Loeliger <[email protected]>
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The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.
Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.
Signed-off-by: Trent Piepho <[email protected]>
Acked-by: Kumar Gala <[email protected]>
Acked-by: Jon Loeliger <[email protected]>
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On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <[email protected]>
Acked-by: Kumar Gala <[email protected]>
Acked-by: Jon Loeliger <[email protected]>
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Removed initialization of the driver from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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Affected boards:
Several MPC8xx boards
Several MPC8260/MPC8272 boards
Several MPC85xx boards
Removed initialization of the driver from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC
Signed-off-by: Ben Warren <[email protected]>
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Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Ed Swarthout <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.
Signed-off-by: Jason Jin <[email protected]>
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Signed-off-by: Sergei Poselenov <[email protected]>
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The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Ben Warren <[email protected]>
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The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We
also have SERDES init code for the 8536.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Dejan Minic <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kim Phillips <[email protected]>
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This patch is the first step in cleaning up net/eth.c, by moving Ethernet
initialization to CPU or board-specific code. Initial implementation is
only on the Freescale TSEC controller, but others will be added soon.
Signed-off-by: Ben Warren <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Building for 4xx doesn't work since commit 4dbdb768:
In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1
This patch fixes the problem.
Signed-off-by: Anatolij Gustschin <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Acked-by: Kumar Gala <[email protected]>
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Signed-off-by: Sergei Poselenov <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The boot output is now aligned poperly with other boot output
lines, e.g.:
FLASH: 128 MB
L2: 512 KB enabled
Signed-off-by: Wolfgang Grandegger <[email protected]>
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The current cpu identification code is used just to return the name
of the processor at boot. There are some other locations that the name
is useful (device tree setup). Expose the functionality to other bits
of code.
Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out. This is mainly to allow the most flexible use
of the name. The device tree code tends to not care about the 'E' suffix.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Sergei Poselenov <[email protected]>
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eg. because of rounding error we can get 799Mhz instead of 800Mhz.
Introduced DIV_ROUND_UP and roundup taken from linux kernel.
Signed-off-by: Dejan Minic <[email protected]>
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Andy Fleming <[email protected]>
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Show the DDR memory data rate in addition to the memory clock
frequency. For DDR/DDR2 memories the memory data rate is 2x the
memory clock.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t. Fix
rounding of result to nearest; previously it was rounding
upwards.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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FSL has taken to using SVR[16:23] as an SOC sub-version field. This
is used to distinguish certain variants within an SOC family. To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value. We also add SVR numbers for all
of the current variants. Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.
Signed-off-by: Andy Fleming <[email protected]>
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The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: Kumar Gala <[email protected]>
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