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By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Stefan Roese <[email protected]>
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This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:
src/soc/intel/fsp_baytrail/chip.h
(git ID da1a70ea from 2016-01-16 as reference).
Signed-off-by: Stefan Roese <[email protected]>
Cc: Andrew Bradford <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <[email protected]>
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Fix a small typo in this binding file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Describe all required properties needed by the irq router device tree.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).
Signed-off-by: Simon Glass <[email protected]>
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The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <[email protected]>
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This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.
Signed-off-by: Bernie Thompson <[email protected]>
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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