| Age | Commit message (Collapse) | Author |
|---|
|
Add socfpga_dtreg driver enablement for Intel SoCFPGA.
Signed-off-by: Wan Yee Lau <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Move esm-k3.txt to ti,j721e-esm.yaml in line with the devicetree
documentation in kernel.
Signed-off-by: Neha Malcom Francis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Now that Linux has accepted these tags, move U-Boot over to use them.
Signed-off-by: Simon Glass <[email protected]>
|
|
Document trivial bindings for atsha204 and atsha204a.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
K3 J721E:
* OSPI boot support
* Support for loading remote cores in R5 SPL
* PMIC ESM Support
* Minor fixes for R5F and C7x remoteproc drivers
K3 AM654:
* Update AVS class 0 voltages.
* Add I2C nodes
DRA7xx/AM57xx:
* Fixed Android boot on AM57xx
AM33/AM43/Davinci:
* switch to driver model for the net and mdio driver for baltos
* Add DM/DTS support for omap video driver
* Enable fastboot on am335x-evm
|
|
add DM/DTS support for the memory based bootcounter
in drivers/bootcount/bootcount.c.
Let the old implementation in, so boards which have
not yet convert to DM/DTS do not break.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.
Signed-off-by: Tero Kristo <[email protected]>
|
|
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.
Signed-off-by: Tero Kristo <[email protected]>
|
|
Commit ad7061ed742e ("doc: Move device tree bindings documentation to
doc/device-tree-bindings") moved all device tree binding documentation
to doc/device-tree-bindings directory.
The current U-Boot project still have two documentation directories:
- doc/
- Documentation/
Move all documentation and sphinx files to doc directory so all content
can be in a common place.
Signed-off-by: Breno Lima <[email protected]>
|
|
Add a document to describe file system firmware loader binding
information.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Stefan Roese <[email protected]>
|
|
This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:
src/soc/intel/fsp_baytrail/chip.h
(git ID da1a70ea from 2016-01-16 as reference).
Signed-off-by: Stefan Roese <[email protected]>
Cc: Andrew Bradford <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <[email protected]>
|
|
Fix a small typo in this binding file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Describe all required properties needed by the irq router device tree.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).
Signed-off-by: Simon Glass <[email protected]>
|
|
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <[email protected]>
|
|
This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.
Signed-off-by: Bernie Thompson <[email protected]>
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
