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The current implementation configures RGMII using device tree phy-mode
property and then calls genphy_config
adin_config_rgmii_mode is derived from:
https://github.com/varigit/linux-imx/blob/lf-5.10.y_var04/drivers/net/phy/adin.c#L218-L262
Signed-off-by: Nate Drude <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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The correct name for the property is "qca,clk-out-frequency", so fix
it accordingly.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
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Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.
Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.
Signed-off-by: Michael Walle <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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