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path: root/drivers/clk/mediatek/clk-mt8188.c
AgeCommit message (Expand)Author
2026-03-24clk: mediatek: mt8188: convert CLK_XTAL to CLK_PAD_CLK26MDavid Lechner
2026-03-24clk: mediatek: replace xtal2_rate with struct mtk_parentDavid Lechner
2026-03-24clk: mediatek: mt8188: use ext_clock_ratesDavid Lechner
2026-03-24clk: mediatek: remove CLK_PARENT_MIXED flagDavid Lechner
2026-03-24clk: mediatek: mt8188: convert to struct mtk_parentDavid Lechner
2026-03-17clk: mediatek: rename HAVE_RST_BARDavid Lechner
2026-03-17clk: mediatek: mt8188: fix CLK_TOP_CLK{13,26}M ratesDavid Lechner
2026-02-18clk: mediatek: mt8188: refactor driver to improve readabilityJulien Stephan
2026-02-18clk: mediatek: mt8188: fix some clock parentsJulien Stephan
2026-02-18clk: mediatek: mt8188: add missing fixed clockJulien Stephan
2026-02-18clk: mediatek: mt8188: fix circular clock dependencyJulien Stephan
2026-02-18clk: mediatek: mt8188: remove separate topckgen-cg driverJulien Stephan
2026-01-12clk: mediatek: fix fixed clock parentsDavid Lechner
2026-01-12clk: mediatek: add separate gates_offs for cg gatesDavid Lechner
2026-01-12clk: mediatek: add array size field for id_offs_mapDavid Lechner
2026-01-12clk: mediatek: add array size fields to cg gatesDavid Lechner
2026-01-12clk: mediatek: add array size fields to clk treesDavid Lechner
2026-01-06clk: mediatek: add MT8188 clock driverJulien Masson
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-13 12:17:03 +0000