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The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the
QSPI clocks in this case to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <[email protected]>
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The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the
ecspi clocks in this case to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <[email protected]>
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Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock
inside the non-SPL block to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <[email protected]>
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PWM is not used inside SPL, so do not define the PWM clocks inside
SPL to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.01-rc1 (round 3)
fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure
zynq:
- Enable early EEPROM decoding
- Some DT updates
zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates
net:
- emaclite: Enable driver for RISC-V
xilinx:
- Fix static checker warnings
- Fix GCC12 warning
sdhci:
- Read PD id from DT
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Fix the following sparse and compile time warning
triggered with W=1:
drivers/clk/clk_versal.c:605:5:
warning: no previous prototype for 'versal_clock_setup'
[-Wmissing-prototypes]
605 | int versal_clock_setup(void)
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add gpmi nand clock. Those clock can be used in mxs nand driver
to run nand to EDO mode 5, 4, ...
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Add shared counter in order to avoid to swich off clock that
are already used.
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Add clock controller driver for NPCM845
Signed-off-by: Jim Liu <[email protected]>
Acked-by: Sean Anderson <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
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Add support for Versal NET compatible string in clock driver.
Signed-off-by: Jay Buddhabhatti <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
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This patch adds clock driver support for MediaTek MT7981 SoC
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds clock driver support for MediaTek MT7986 SoC
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds infrasys clock mux support for mediatek clock drivers.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds support for a clock node to configure its parent clock
where possible.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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parent of xtal clock
The mtk clock framework in u-boot uses array index for searching clock
parent (kernel uses strings for search), so we need to specify a special
clock with ID=0 for CLK_XTAL in u-boot.
In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
expected.
However for newer chips, they may have some clocks with ID=0 not
representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
called. Current logic will make entire clock driver not working.
This patch adds a flag to indicate that whether a clock driver needs clocks
with ID=0 to call mtk_topckgen_get_mux_rate.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.01 cycle:
This feature set includes the important update on PIO4 pinctrl driver
that solves a long time mismatch between Linux and U-boot, related on
the unification of pinctrl and gpio driver support, now respecting the
pinctrl bindings ABI; and also support for pinctrl subnodes. The feature
set also adds support for PDA screen detection for sam9x60_curiosity
board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
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Signed-off-by: Tom Rini <[email protected]>
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ddrck and qspick should have mck_div as parent clocks to be in sync with
linux driver.
Signed-off-by: Mihai Sain <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
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Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube <[email protected]>
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The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube <[email protected]>
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User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
- simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
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Handle the input clock of RCC USB_PHY_48, provided by USBPHYC
and named "ck_usbo_48m".
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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This commit sychronizes the header file for FU740 PRCI clocks with the
one from Linux 5.19.
The constant values are the same, but all constant names are changed
(most are just prefixed with FU740_).
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Adding some debug prints I can see:
MMC: mmc@fe320000: Got clock clock-controller@ff760000 76
mmc@fe310000: Got clock clock-controller@ff760000 77
Unknown clock 77
rockchip_dwmmc_get_mmc_clk: err=-2
mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0
According to kernel code the SDIO clock is identical to SDMMC clock
except for the con 16->15 change.
Add support for the clock to avoid the error.
Signed-off-by: Michal Suchanek <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Fix diacritics in some instances of my name and change my e-mail address
to [email protected].
Add corresponding .mailmap entries.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The clock and reset drivers use the exact same platform data. Simplify
them by sharing the object. This is safe because the parent device
(the clock device) always gets its driver model callbacks run first.
Signed-off-by: Samuel Holland <[email protected]>
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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All of the driver private data should really be platform data since it
is determined statically (selected by the compatible string or extracted
from the devicetree). Move everything to platform data, so it can be
provided when binding the driver. This is useful for SPL, or for
instantiating the driver as part of an MFD.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Now that all of the variants use the same bind/probe functions and ops,
there is no need to have a separate driver for each variant. Since most
SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
of firmware size and RAM.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <[email protected]>
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This allows all of the clock drivers to use a common bind function.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <[email protected]>
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Because the gate arrays are not given explicit sizes, the arrays are
only as large as the highest-numbered gate described in the driver.
However, only a subset of the CCU clocks are needed by U-Boot. So there
are valid clock specifiers with indexes greater than the size of the
arrays. Referencing any of these clocks causes out-of-bounds access.
Fix this by checking the identifier against the size of the array.
Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver")
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The reset array size is currently used for bounds checking in the reset
driver. The same bounds check should really be done in the clock driver.
Currently, the array size is provided to the reset driver separately
from the CCU descriptor, which is a bit strange. Let's do this the usual
way, with the array sizes next to the arrays themselves.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <[email protected]>
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This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Reviewed-by: Sean Anderson <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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In order to use the clock from the sdhci driver, add the SD clock.
Signed-off-by: Joel Stanley <[email protected]>
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Adjust clock to stay compatible with those used by the Linux kernel
device tree.
Signed-off-by: Joel Stanley <[email protected]>
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A common message across platforms that prints the clock number.
Signed-off-by: Joel Stanley <[email protected]>
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All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.
Signed-off-by: Teik Heng Chong <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Compatible strings for some new RTC hardware variants were added to
the binding. Add them to the driver in preparation for supporting
those new SoCs.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Update SCMI clock driver to get its assigned SCMI channel during
initialization. This change allows SCMI clock protocol to use a
dedicated channel when defined in the DT. The reference is saved
in SCMI clock driver private data.
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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Changes SCMI driver API function devm_scmi_process_msg() to add
an SCMI channel reference argument for when SCMI agent supports
SCMI protocol specific channels. First argument of devm_scmi_process_msg()
is also change to point to the caller SCMI protocol device rather
than its parent device (the SCMI agent device).
The argument is a pointer to opaque struct scmi_channel known from
the SCMI transport drivers. It is currently unused and caller a pass
NULL value. A later change will enable such support once SCMI protocol
drivers have means to get the channel reference during initialization.
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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Merge in v2022.07-rc5.
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Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Grzegorz Szymaszek <[email protected]>
Acked-by: Sean Anderson <[email protected]>
Change-Id: I955af307963f732167396f0157a30cf2fc91f150
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Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
HSIOMIX clock") added usb_core_ref for USB Controller but never set it
to be used as a clock source, using rather "osc_32k" instead.
This produces following boot log message:
"clk_register: failed to get osc_32k device (parent of usb_root_clk)"
Fix the USB controller clock source by using usb_core_ref instead of
osc_32k.
Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Andrey Zhizhikin <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Root clock name contained underscore, which does not match to the actual
clock name.
Correct the name to match what is present in the FDT.
Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: uboot-imx <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Introduce autogenerated SoC data support clk and device data for the
AM62. Hook it upto to power-domain and clk frameworks of U-Boot.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========
Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.
Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
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