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https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek
* Clock fix for MT8188 (Genio 700/520)
* SPL support preparatory patch for MT8188.
* Compile error fix for when enabling LWIP network stack on some MediaTek targets.
* Fix a regression in clock driver binding from the previous PR.
* Add display-related clocks on MT8188.
* Another wave of clock driver refactoring and de-duplication.
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Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.
Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.
Signed-off-by: Julien Stephan <[email protected]>
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators.
The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.
Losely based on Linux 7.1 commit
5ec820fc28d0 ("clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841")
Signed-off-by: Marek Vasut <[email protected]>
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driver
The SCMI IDs did not change between SDK SCP 4.32 and SDK SCP 4.36.
Add SDK SCP 4.36 as supported version and reuse SDK SCP 4.32 remap
table.
Signed-off-by: Marek Vasut <[email protected]>
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Parent lookup now probes the exact missing provider on demand, making the
eager probing of every parent provider after bind redundant. The common
bind callback also occupies a driver callback that a provider may need
for unrelated setup.
Remove the common bind callback and its use from all MediaTek parent
providers. Providers are now registered only when first needed or when
normal driver-model probing reaches them.
Signed-off-by: Carlo Caione <[email protected]>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-2-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MediaTek clock trees can reference parents provided by a different clock
controller. The provider registry is populated when each controller
probes, so an early consumer can request a parent before its provider has
been registered.
When lookup misses, find the MediaTek clock device whose operations and
clock-tree type match the requested provider, then probe that device.
This removes the probe-order dependency without probing unrelated clock
controllers or treating a driver's bind callback as a type marker.
Co-developed-by: David Lechner <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-1-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add display related clock drivers, needed for HDMI support.
Signed-off-by: Chris-QJ Chen <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-mt8188-add-clk-add-display-related-clocks-v2-1-0aaf7accaeb0@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Every clock driver now stores its struct mtk_clk_tree in the compatible
data. Rename mtk_common_clk_init() to mtk_clk_probe() and make if fetch
the tree from dev_get_driver_data() instead of taking it as an argument,
so it matches the driver .probe prototype and can be used directly as
the probe callback.
Drop all the per-SoC probe wrappers that only forwarded the driver data
to mtk_clk_probe(), and point the corresponding drivers at
mtk_clk_probe() directly. The few controllers that still need a
dedicated probe for SoC specific register tweaks (some apmixedsys and
topckgen instances) keep it, but now call the single-argument
mtk_clk_probe().
This touches every MediaTek clock driver at once to keep the tree building
across the whole series.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-32-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (renamed mtk_common_clk_init() to mtk_clk_probe())
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Now that every MediaTek SoC describes its clock gates through struct
mtk_clk_tree and handles them with the generic topckgen ops, nothing uses
the dedicated clock gate code path anymore.
Remove struct mtk_cg_priv, the mtk_clk_gate_ops (of_xlate/enable/disable/
get_rate/dump) and mtk_common_clk_gate_init() from clk-mtk. Clock gate
controllers are now just regular mtk_clk_tree providers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-31-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8189 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys, topckgen and vlpckgen controllers keep their own
U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind()
callback, but they now get their tree from the compatible data, like the
clock gate controllers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-30-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8189 already shares a single U_BOOT_DRIVER across all its clock gate
controllers, passing the per-controller gate table through the driver data
via a dedicated struct mt8189_gate_clk_data.
Now that struct mtk_clk_tree can describe the gates directly, drop that
bespoke helper: give each controller its own struct mtk_clk_tree
(.gates/.num_gates/.gates_offs) and use the generic mtk_clk_topckgen_ops.
The gate offset, previously computed at runtime from the first gate ID, is
now encoded statically in each tree.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-29-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (dropped _gates_offs arg from GATE_CLK_TREE)
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8512 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-28-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8512 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for the topckgen and infracfg clock gate controllers, despite both
sharing the same implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Both controllers share the same DM flags and (absent)
bind() callback and are merged into a single U_BOOT_DRIVER.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-27-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8365 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-26-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-25-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8195 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-24-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg_ao gates directly in a struct mtk_clk_tree, reference
the tree from the driver data and use the generic mtk_clk_topckgen_ops
instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-23-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8518 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-22-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-21-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8516 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-20-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-19-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8183 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-18-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-17-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7988 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-16-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7988 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethdma and ethwarp keep their own drivers since they bind reset controllers
at different offsets.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-15-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7987 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-14-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-13-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7986 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-12-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-11-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7981 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-10-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7981 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethsys keeps its own driver as it binds a reset controller.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-9-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7629 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-8-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7629 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Controllers that share the same DM flags and bind()
callback are then merged: infracfg and pericfg into one pre-relocation
driver, sgmiisys and ssusbsys into another. ethsys keeps its own driver as
it binds a reset controller.
While at it, this fixes a latent off-by-one in the infracfg gate lookup: its
clock IDs start at CLK_INFRA_DBGCLK_PD (1), but the old code passed a gate
offset of 0, so requesting e.g. CLK_INFRA_TRNG_PD resolved to the wrong
gate. The offset is now taken from the first gate ID, like the other
controllers.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-7-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7623 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-6-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7623 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The ethsys and hifsys controllers, which share the
same reset-binding bind() callback, are merged into a single U_BOOT_DRIVER;
infracfg keeps its own driver since it is pre-relocation and does not bind a
reset controller.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-5-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7622 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks. The infracfg and pericfg controllers share
the same ops, flags and (absent) bind() callback and are merged into a
single driver.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-4-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7622 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Clock gate controllers that share the same DM flags
and bind() callback can then share a single U_BOOT_DRIVER: the pciesys and
ethsys controllers, which both bind a reset controller at the same offset,
are merged into one driver, and the sgmiisys and ssusbsys controllers into
another.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-3-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (changed to CONFIG_IS_ENABLED)
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Pass each controller's struct mtk_clk_tree through the driver data and use
a single shared probe function for all the MT8188 clock drivers, instead of
a dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
share the generic probe and get their tree from the compatible data, just
like the clock gate controllers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-2-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8188 currently declares a separate U_BOOT_DRIVER, probe() function and
compatible table for each clock gate controller, despite all of them
sharing the same implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. All the clock gate controllers can then share a
single U_BOOT_DRIVER, eliminating the duplicated code.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Suggested-by: David Lechner <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-1-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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The Allwinner sun55i (A523/A527/T527) platform requires the MBUS clock
gate enabled for the gmac1 controller to function. Add the clock gate
definition for CLK_MBUS_EMAC1.
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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Change driver names for MediaTek mt8518 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-15-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8516 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-14-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8512 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-13-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8365 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-12-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8195 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-11-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8189 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-10-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8188 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-9-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt8183 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-8-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt7988 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-7-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change driver names for MediaTek mt7987 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-6-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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