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2022-11-15clk: microchip: mpfs: fix criticality of peripheral clocksConor Dooley
Sync the critical clocks in the U-Boot driver with those marked as critical in Linux. The Linux driver has an explanation of why each clock is considered to be critical, so import that too. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]> Reviewed-by: Padmarao Begari <[email protected]>
2022-11-15clk: microchip: mpfs: fix periph clk parentageConor Dooley
Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]> Reviewed-by: Padmarao Begari <[email protected]> Tested-by: Padmarao Begari <[email protected]>
2022-11-15clk: microchip: mpfs: fix reference clock handlingConor Dooley
The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]> Reviewed-by: Padmarao Begari <[email protected]> Tested-by: Padmarao Begari <[email protected]>
2022-11-15clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()Conor Dooley
Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]> Reviewed-by: Padmarao Begari <[email protected]>
2022-10-24Merge tag 'u-boot-imx-20221024' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20221024 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916 - for 2022.01 - rework Kontron boards (mx6 and mx8) - fixes for Toradex - fixes (SPI, CAAM, ) - sync DT with Linux - fixes for Gateworks GW7903 and GW7904 PMIC - Engicam i.Core MX8M Plus EDIMM2.2
2022-10-21clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=yFabio Estevam
The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the QSPI clocks in this case to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <[email protected]>
2022-10-21clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=yFabio Estevam
The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the ecspi clocks in this case to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <[email protected]>
2022-10-21clk-imx8mm: Move CLK_ENET_AXI to the non-SPL sectionFabio Estevam
Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock inside the non-SPL block to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <[email protected]>
2022-10-21clk-imx8mm: Only build PWM clocks in non-SPL codeFabio Estevam
PWM is not used inside SPL, so do not define the PWM clocks inside SPL to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <[email protected]>
2022-10-20Merge tag 'u-boot-rockchip-20221020' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - dts update and sync for rk356x, rk3288, rk3399 from Linux; - Add rk3399 EAIDK-610 board support; - Update for puma-rk3399 board; - some fix and typo fix in different drivers;
2022-10-20Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2022-10-20Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clkTom Rini
Clock patches for 2023.01 This contains various fixes (some long overdue) for the next release.
2022-10-20k210: fix k210_pll_calc_config()Heinrich Schuchardt
The k210 driver is selected by sandbox_defconfig. Building the sandbox on 32bit systems fails with: test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’: include/linux/bitops.h:11:38: warning: left shift count >= width of type [-Wshift-count-overflow] 11 | #define BIT(nr) (1UL << (nr)) | ^~ test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’ 36 | error = abs((error - BIT(32))) >> 16; | ^~~ Use the BIT_ULL() macro to create a u64 value. Replace abs() by abs64() to get correct results on 32bit system Apply the same for the unit test. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2022-10-19clk: update clk_clean_rate_cache to use private clk structPatrick Delaunay
In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-10-19rockchip: clk: pll: Fix constant typoMichal Suchanek
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by: Michal Suchanek <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-10-19clk: change return type of clk_get_parent_rate from long long to ulongMichal Suchanek
All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Michal Suchanek <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-10-19arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented rangeXavier Drudis Ferran
The original code set up the DDR clock to 48 MHz, not 50MHz as requested, and did it in a way that didn't satisfy the Application Notes in RK3399 TRM [1]. 2.9.2.B says: PLL frequency range requirement [...] FOUTVCO: 800MHz to 3.2GHz 2.9.2.A : PLL output frequency configuration [...] FOUTVCO = FREF / REFDIV * FBDIV FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 FREF = 24 MHz The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz but the requested frequency was 50MHz Note: 2.7.2 Detail Register Description PMUCRU_PPLL_CON0 says fbdiv Feedback Divide Value Valid divider settings are: [16, 3200] in integer mode So .fbdiv = 12 wouldn't be right. But 2.9.2.C says: PLL setting consideration [...] The following settings are valid for FBDIV: DSMPD=1 (Integer Mode): 12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600 (FVCOMAX / FREFMIN)) [...] So .fbdiv = 12 would be right. In any case FOUTVCO is still wrong. I thank YouMin Chen for confirmation and explanation. Despite documentation, I don't seem to be able to reproduce a practical problem with the wrong FOUTVCO. When I initially found it I thought some problems with detecting the RAM capacity in my Rock Pi 4B could be related to it and my patch seemed to help. But since I'm no longer able to reproduce the issue, it works with or without this patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses this issue. Btw, shouldn't that be commited? So this patches solves no visible problem. Yet, to prevent future problems, I think it'd be best to stick to spec. An alternative to this patch could be {.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6}; This would theoretically consume more power and yield less jitter, according to 2.9.2.C : PLL setting consideration [...] For lowest power operation, the minimum VCO and FREF frequencies should be used. For minimum jitter operation, the highest VCO and FREF frequencies should be used. [...] But I haven't tried it because I don't think it matters much. 50MHz for DDR is only shortly used by TPL at RAM init. Normal operation is at 800MHz. Maybe it's better to use less power until later when more complex software can control batteries or charging or whatever ? Cc: Simon Glass <[email protected]> Cc: Philipp Tomsich <[email protected]> Cc: Kever Yang <[email protected]> Cc: Lukasz Majewski <[email protected]> Cc: Sean Anderson <[email protected]> Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766 Signed-off-by: Xavier Drudis Ferran <[email protected]> Tested-by: Michal Suchánek <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-10-11Merge tag 'xilinx-for-v2023.01-rc1-v3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc1 (round 3) fpga: - Create new uclass - Get rid of FPGA_DEBUG and use logging infrastructure zynq: - Enable early EEPROM decoding - Some DT updates zynqmp: - Use OCM_BANK_0 to check config loading permission - Change config object loading in SPL - Some DT updates net: - emaclite: Enable driver for RISC-V xilinx: - Fix static checker warnings - Fix GCC12 warning sdhci: - Read PD id from DT
2022-10-10clk: versal: Mark versal_clock_setup() as staticVenkatesh Yadav Abbarapu
Fix the following sparse and compile time warning triggered with W=1: drivers/clk/clk_versal.c:605:5: warning: no previous prototype for 'versal_clock_setup' [-Wmissing-prototypes] 605 | int versal_clock_setup(void) Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-10-09clk: imx: clk-imx8mn add gpmi nand clocksMichael Trimarchi
Add gpmi nand clock. Those clock can be used in mxs nand driver to run nand to EDO mode 5, 4, ... Signed-off-by: Michael Trimarchi <[email protected]> Reviewed-by: Dario Binacchi <[email protected]> Signed-off-by: Dario Binacchi <[email protected]>
2022-10-09clk: imx: gate2 support shared counter and relative clock functionsMichael Trimarchi
Add shared counter in order to avoid to swich off clock that are already used. Signed-off-by: Michael Trimarchi <[email protected]> Reviewed-by: Dario Binacchi <[email protected]> Signed-off-by: Dario Binacchi <[email protected]>
2022-10-06clk: nuvoton: Add support for NPCM845Jim Liu
Add clock controller driver for NPCM845 Signed-off-by: Jim Liu <[email protected]> Acked-by: Sean Anderson <[email protected]>
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
2022-09-26clk: versal: Enable clock driver for Versal NETJay Buddhabhatti
Add support for Versal NET compatible string in clock driver. Signed-off-by: Jay Buddhabhatti <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
2022-09-23clk: mediatek: add clock driver support for MediaTek MT7981 SoCWeijie Gao
This patch adds clock driver support for MediaTek MT7981 SoC Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-23clk: mediatek: add clock driver support for MediaTek MT7986 SoCWeijie Gao
This patch adds clock driver support for MediaTek MT7986 SoC Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Tested-by: Daniel Golle <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-23clk: mediatek: add CLK_XTAL support for clock driverWeijie Gao
This adds the CLK_XTAL macro/flag to allow modeling clocks which are directly connected to the xtal clock. Reviewed-by: Simon Glass <[email protected]> Tested-by: Daniel Golle <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-23clk: mediatek: add infrasys clock mux supportWeijie Gao
This patch adds infrasys clock mux support for mediatek clock drivers. Reviewed-by: Simon Glass <[email protected]> Tested-by: Daniel Golle <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-23clk: mediatek: add support to configure clock driver parentWeijie Gao
This patch adds support for a clock node to configure its parent clock where possible. Reviewed-by: Simon Glass <[email protected]> Tested-by: Daniel Golle <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-23clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock ↵Weijie Gao
parent of xtal clock The mtk clock framework in u-boot uses array index for searching clock parent (kernel uses strings for search), so we need to specify a special clock with ID=0 for CLK_XTAL in u-boot. In the mt7622/mt7629 clock tree, the clocks with ID=0 never call mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we expected. However for newer chips, they may have some clocks with ID=0 not representing the xtal clock and still needs mtk_topckgen_get_mux_rate be called. Current logic will make entire clock driver not working. This patch adds a flag to indicate that whether a clock driver needs clocks with ID=0 to call mtk_topckgen_get_mux_rate. Reviewed-by: Simon Glass <[email protected]> Tested-by: Daniel Golle <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-09-20Merge tag 'u-boot-at91-2023.01-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.01 cycle: This feature set includes the important update on PIO4 pinctrl driver that solves a long time mismatch between Linux and U-boot, related on the unification of pinctrl and gpio driver support, now respecting the pinctrl bindings ABI; and also support for pinctrl subnodes. The feature set also adds support for PDA screen detection for sam9x60_curiosity board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <[email protected]>
2022-09-19clk: at91: sam9x60: change parent clock from mck_pres to mck_divMihai Sain
ddrck and qspick should have mck_div as parent clocks to be in sync with linux driver. Signed-off-by: Mihai Sain <[email protected]> Reviewed-by: Claudiu Beznea <[email protected]>
2022-09-18clk: imx: Add initial support for i.MXRT1170 clock driverJesse Taube
Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube <[email protected]>
2022-09-18clk: imx: Add i.MXRT11xx pllv3 variantJesse Taube
The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube <[email protected]>
2022-09-13clk: aspeed: Get HCLK frequency supportChin-Ting Kuo
User can get correct HCLK frequency during driver probe stage by adding the following configuration in the device tree. "clocks = <&scu ASPEED_CLK_AHB>". Signed-off-by: Chin-Ting Kuo <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]>
2022-09-08Merge tag 'u-boot-stm32-20220907' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - simplify the STM32MP15x package parsing code - remove test on CONFIG_DM_REGULATOR in stm32mp1 board and enable CONFIG_DM_REGULATOR for stm32f769-disco - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start' after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>) - Fix SYS_HZ_CLOCK value for stih410-b2260 board - Switch STMM32MP15x DHSOM to FMC2 EBI driver - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
2022-09-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2022-09-06clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYCPatrick Delaunay
Handle the input clock of RCC USB_PHY_48, provided by USBPHYC and named "ck_usbo_48m". Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2022-09-06dt-bindings: clock: sifive: sync FU740 PRCI clock binding headerIcenowy Zheng
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2022-09-04clk: rockchip: rk3399: Fix Unknown clock 77 on mmc@fe310000Michal Suchanek
Adding some debug prints I can see: MMC: mmc@fe320000: Got clock clock-controller@ff760000 76 mmc@fe310000: Got clock clock-controller@ff760000 77 Unknown clock 77 rockchip_dwmmc_get_mmc_clk: err=-2 mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 According to kernel code the SDIO clock is identical to SDMMC clock except for the con 16->15 change. Add support for the clock to avoid the error. Signed-off-by: Michal Suchanek <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-07-21treewide: Fix Marek's name and change my e-mail addressMarek Behún
Fix diacritics in some instances of my name and change my e-mail address to [email protected]. Add corresponding .mailmap entries. Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-07-18reset: sunxi: Reuse the platform data from the clock driverSamuel Holland
The clock and reset drivers use the exact same platform data. Simplify them by sharing the object. This is safe because the parent device (the clock device) always gets its driver model callbacks run first. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2022-07-18clk: sunxi: Convert driver private data to platform dataSamuel Holland
All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2022-07-18clk: sunxi: Use a single driver for all variantsSamuel Holland
Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <[email protected]>
2022-07-18reset: sunxi: Get the reset count from the CCU descriptorSamuel Holland
This allows all of the clock drivers to use a common bind function. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <[email protected]>
2022-07-18clk: sunxi: Prevent out-of-bounds gate array accessSamuel Holland
Because the gate arrays are not given explicit sizes, the arrays are only as large as the highest-numbered gate described in the driver. However, only a subset of the CCU clocks are needed by U-Boot. So there are valid clock specifiers with indexes greater than the size of the arrays. Referencing any of these clocks causes out-of-bounds access. Fix this by checking the identifier against the size of the array. Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver") Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2022-07-18clk: sunxi: Store the array sizes in the CCU descriptorSamuel Holland
The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <[email protected]>
2022-07-13clk: mtmips: add clock driver for MediaTek MT7621 SoCWeijie Gao
This patch adds a clock driver for MediaTek MT7621 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Sean Anderson <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2022-07-11Merge branch 'next'Tom Rini
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