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2020-07-14clk: imx8m: drop clk settingsPeng Fan
We use non-dm code to configure the clk settings in order to simplify dm clk driver in future, so remove the duplicated code from clk driver Signed-off-by: Peng Fan <[email protected]>
2020-07-14clk: imx8mp: Update imx8mp ccf clock driverYe Li
Add clocks for FEC and flexspi, and add set parent clock callback, so DTS can assign clocks Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2020-07-14clk: imx8mm/8mn: Add USB clocksYe Li
Add USB relevant clocks to support usb clock settings for both DM USB host and gadget drivers Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2020-07-14clk: clk-imx8mn: Update clock tree and support set parentYe Li
Add set clock parent support. Add ENET and flexspi related clocks to support assigned clocks Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2020-07-14clk: imx8mm: Add qspi clockPeng Fan
Add qspi clock Signed-off-by: Peng Fan <[email protected]>
2020-07-14clk: imx8mm: fix clk set parentPeng Fan
Fix clk set parent, so we could still have correct clocks after parent changing. Signed-off-by: Peng Fan <[email protected]>
2020-07-09dtoc: extend dtoc to use struct driver_info when linking nodesWalter Lozano
In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch extends dtoc to use struct driver_info when populating information about linked nodes, which makes it easier to later get the devices created. In this context, reimplement functions like clk_get_by_index_platdata() which made use of the previous approach. Signed-off-by: Walter Lozano <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-07-09core: add support for U_BOOT_DRIVER_ALIASWalter Lozano
Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-07-09drivers: rename drivers to match compatible stringWalter Lozano
When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <[email protected]> Reviewed-by: Simon Glass <[email protected]> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <[email protected]>
2020-07-07clk: actions: Add Ethernet clocksAmit Singh Tomar
This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar <[email protected]>
2020-07-07arm: stm32mp: add weak function to save vddcorePatrick Delaunay
Add a weak functions to save the vddcore voltage value provided in the OPP node when the clock tree is initialized. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2020-07-07stm32mp1: clk: configure pll1 with OPPPatrick Delaunay
The PLL1 node (st,pll1) is optional in device tree, the max supported frequency define in OPP node is used when the node is absent. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2020-07-01dm: Fix error handling for dev_read_addr_ptrSean Anderson
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was enabled. This patch converts both implementations to return NULL on error, and converts all call sites which check for FDT_ADDR_T_NONE to check for NULL instead. This patch also removes the call to map_physmem, since we have dev_remap_addr* for those semantics. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-07-01clk: Add K210 clock supportSean Anderson
Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. Clocks parameters are stored in several arrays, and are then instantiated at run-time. There are some translation macros (FOOIFY()) which allow for more dense packing. Signed-off-by: Sean Anderson <[email protected]> CC: Lukasz Majewski <[email protected]>
2020-07-01clk: Add a bypass clock for K210Sean Anderson
This is a small driver to do a software bypass of a clock if hardware bypass is not working. I have tried to write this in a generic fashion, so that it could be potentially broken out of the kendryte code at some future date. For the K210, it is used to have aclk bypass pll0 and use in0 instead so that the CPU keeps on working. Signed-off-by: Sean Anderson <[email protected]> CC: Lukasz Majewski <[email protected]>
2020-07-01clk: Add K210 pll supportSean Anderson
This pll code is primarily based on the code from the kendryte standalone sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to the algorithm used to set the pll frequency, but it has been completely rewritten to be fixed-point based. Signed-off-by: Sean Anderson <[email protected]> CC: Lukasz Majewski <[email protected]>
2020-07-01clk: Fix clk_get_by_* handling of indexSean Anderson
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean predicate instead of the index. Other clk_get_by_* functions got the clock correctly, but passed a predicate instead of the index to clk_get_by_tail. This could lead to confusing error messages. Signed-off-by: Sean Anderson <[email protected]> CC: Lukasz Majewski <[email protected]>
2020-07-01clk: Check that ops of composite clock components exist before callingSean Anderson
clk_composite_ops was shared between all devices in the composite clock driver. If one clock had a feature (such as supporting set_parent) which another clock did not, it could call a null pointer dereference. This patch does three things 1. It adds null-pointer checks to all composite clock functions. 2. It makes clk_composite_ops const and sets its functions at compile-time. 3. It adds some basic sanity checks to num_parents. The combined effect of these changes is that any of mux, rate, or gate can be NULL, and composite clocks will still function normally. Previously, at least mux had to exist, since clk_composite_get_parent was used to determine the parent for clk_register. Signed-off-by: Sean Anderson <[email protected]> Acked-by: Lukasz Majewski <[email protected]>
2020-07-01clk: Always use the supplied struct clkSean Anderson
CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite clock did not have the ->dev field filled in. This was fine, because the device-specific clock information would be used. However, since there was no ->dev, there was no way to get the parent clock. This caused the recalc_rate method of the CCF divider clock to fail. One option would be to use the clk->priv field to get the composite clock and from there get the appropriate parent device. However, this would tie the implementation to the composite clock. In general, different devices should not rely on the contents of ->priv from another device. The simple solution to this problem is to just always use the supplied struct clock. The composite clock now fills in the ->dev pointer of its child clocks. This allows child clocks to make calls like clk_get_parent() without issue. imx avoided the above problem by using a custom get_rate function with composite clocks. Signed-off-by: Sean Anderson <[email protected]> Acked-by: Lukasz Majewski <[email protected]>
2020-06-30Merge tag 'mips-pull-2020-06-29' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next - net: pcnet: cleanup and add DM support - Makefile: add rule to build an endian-swapped U-Boot image used by MIPS Malta EL variants - CI: add Qemu tests for MIPS Malta
2020-06-27rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2020-06-24clk: versal: Remove alt_ref_clk from clock sourcesRajan Vaja
alt_ref_clk is applicable only for PS extended version. For PS base version there is no separate alt_ref_clk. It is tied with ref_clk, so remove it from driver. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2020-06-04clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel
U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]>
2020-06-04clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel
Release ddr clock reset once clock is initialized Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]>
2020-06-04clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel
Added clock enable and disable functions in prci ops Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]> Acked-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]>
2020-05-29clk: rk3399: Enable/Disable TCPHY clocksJagan Teki
Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2020-05-29clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2020-05-29clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki
Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2020-05-29clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki
Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2020-05-22clk: rk3399: Enable/Disable the PCIEPHY clkJagan Teki
Enable/Disable the PCIEPHY clk for rk3399. CLK is clear in both enable and disable functionality. Signed-off-by: Jagan Teki <[email protected]> Tested-by: Suniel Mahesh <[email protected]> #roc-rk3399-pc Reviewed-by: Kever Yang <[email protected]>
2020-05-22clk: rk3399: Add enable/disable clksJagan Teki
Yes, most of the high speed peripheral clocks in rk3399 enabled by default. But it would be better to handle them via clk enable/disable API for handling proper reset conditions like 'usb reset' over command line. So, enable USB, GMAC clock via enable/disable ops. Signed-off-by: Jagan Teki <[email protected]> Tested-by: Suniel Mahesh <[email protected]> # roc-rk3399-pc Tested-by: Suniel Mahesh <[email protected]> #roc-rk3399-pc Reviewed-by: Kever Yang <[email protected]>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop linux/stringify.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop linux/bug.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop asm/ptrace.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop log.h from common headerSimon Glass
Move this header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18command: Remove the cmd_tbl_t typedefSimon Glass
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop init.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <[email protected]>
2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <[email protected]>
2020-05-14Merge tag 'u-boot-stm32-20200514' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
2020-05-14clk: stm32mp1: fix CK_MPU calculationLionel Debieve
When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter PLL_MPUDIV. Signed-off-by: Lionel Debieve <[email protected]> Signed-off-by: Patrick Delaunay <[email protected]>
2020-05-13CLK: ARC: HSDK: add separate clock map for HSDK-4xDEugeniy Paltsev
HSDK and HSDK-4xD clock trees are slightly different. commit 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") introduce regression for HSDK board cause crash when setting tunnel clock. Fix that. Fixes: 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: define clock map with DT binding constantsEugeniy Paltsev
Define clock map with DT binding constants so clock map can be discontinuous. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: make set_clock optionalEugeniy Paltsev
We don't want to allow change some clocks, i.e. DDR clock. So allow to have set_clock to be unset in clock map. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: prepare for multiple clock maps supportEugeniy Paltsev
The clock trees of HSDK and HSDK-4xD vary so we need to prepare CGU driver for multiple clock maps support. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: driver cleanupEugeniy Paltsev
Minor code cleanup to improve readability. No functional change intended. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: use appropriate config data typesEugeniy Paltsev
* constify clocks config data where is possible * use more appropriate data types for clocks config Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: drop unused offsetEugeniy Paltsev
Drop creg_div_oft offset as it doesn't vary (due to it is used for CPU PLL only). Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
2020-05-13CLK: ARC: HSDK: avoid code duplicationEugeniy Paltsev
hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures and functions for their processing are almost the same so merge them to avoid code duplication. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
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