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path: root/drivers/clk
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2025-03-27clk: sunxi: Add support for the A100/A133 CCUAndre Przywara
The Allwinner A100 SoC has been around for a while, and has now seemingly been replaced with its close sibling A133. Add support for the CCU, as far as used by U-Boot proper. Linux has some basic (clock and pinctrl) support for a while, so we can already use the existing binding headers. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Jernej Skrabec <[email protected]>
2025-03-25Merge tag 'u-boot-imx-next-20250325' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25324 - Imply the i.MX thermal driver by default on imx8, imx9, imx8m. - Add clk_resolve_parent_clk() and fix up iMX clock drivers.
2025-03-24Merge tag 'qcom-next-20250324' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next qcom-next-20230324: * msm8916 gets proper sysreset and spin-table support * The first new IPQ platform is added - the IPQ9574. The IPQ series are used in routers. The flashing process is also documented * mach-snapdragon gains the ability to boot with an internal FDT and still parse memory from an externally provided one * SC7280 gets a pinctrl driver and various clock driver improvements. * Qualcom clock drivers will now actually return an error when attempting to enable a clock which isn't described. * Qualcomm pinctrl drivers will now return an error when attempting to configure an invalid function mux
2025-03-24clk: imx: Pass struct udevice into imx_clk_fixed_factor*()Marek Vasut
Pass struct udevice * into imx_clk_fixed_factor*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-fixed-factor: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-fixed-factor: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-fixed-factor registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-divider: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice into imx_clk_divider*()Marek Vasut
Pass struct udevice * into imx_clk_divider*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-divider: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-divider clock registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: pllv3: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice into imx_clk_pllv3*()Marek Vasut
Pass struct udevice * into imx_clk_pllv3*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Convert clock-osc-* back to osc_*Marek Vasut
Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k. These are the clock which match clock tables in Linux. This is now possible because the clock drivers now resolve clock names based on clock-names DT property in the CCM DT node. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice into imx_clk_composite*()Marek Vasut
Pass struct udevice * into imx_clk_composite*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-composite: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-composite: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-composite registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice to clk_register_gate*()Marek Vasut
Pass U-Boot specific struct udevice pointer to clock parent device to clk_register_gate*(), so clk_register_gate*() can access the parent udevice. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice into imx_clk_gate*()Marek Vasut
Pass struct udevice * into imx_clk_gate*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: gate2: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: gate2: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in gate2 clock registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-gate: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-gate: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-gate registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice to clk_register_mux()Marek Vasut
Pass U-Boot specific struct udevice pointer to clock parent device to clk_register_mux(), so clk_register_mux() can access the parent udevice. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: imx: Pass struct udevice into imx_clk_mux*()Marek Vasut
Pass struct udevice * into imx_clk_mux*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-mux: Resolve parent clock by nameMarek Vasut
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-mux: Use struct udevice instead of struct deviceMarek Vasut
Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-mux registration. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: clk-mux: Fold clk_register_mux()Marek Vasut
Neither clk_register_mux_table() nor clk_hw_register_mux_table() are called outside of clk-mux.c , fold both into clk_register_mux(). No functional change. Signed-off-by: Marek Vasut <[email protected]>
2025-03-24clk: Add clk_resolve_parent_clk()Marek Vasut
Add clk_resolve_parent_clk() to resolve parent clock udevice name based on clock-names DT property. This is used in SoC clock drivers to look up the clock name in clock tables, which matches a clock name in DT clock-names property, and convert it into udevice name which is used by U-Boot clock framework to look up parent clock in e.g. clk_register() using uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); Signed-off-by: Marek Vasut <[email protected]>
2025-03-19clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MPAdam Ford
If SPL_CLK_IMX8MP is selected alone, it causes a build error. The clock composite is required when using the clock framework, so select it when SPL_CLK_IMX8MP is enabled. This is already being done outside of SPL. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Peng Fan <[email protected]>
2025-03-19clk: imx8mn: register UART clocksAdam Ford
In order to let the serial driver enable the clocks, the UART clocks must be registered first. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Peng Fan <[email protected]>
2025-03-19clk: imx8mm: register UART clocksAdam Ford
In order to let the serial driver enable the clocks, the UART clocks must be registered first. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Peng Fan <[email protected]>
2025-03-19clk: imx6q: Register UART clocksAdam Ford
In order to use the driver model and clock system to enable UART clocks from the serial driver, it's necessary to register the UART clocks. With the helper function to check for imx6qp vs other variants, the UART can register for both scenarios. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Peng Fan <[email protected]>
2025-03-19clk: imx6q: Properly handle imx6qp ECSPI clk_selsAdam Ford
The ECSPI clock has the ability to select between pll3_60m and osc on the imx6qp, where it's fixed on other variants. Fix this by adding using a helper function to determine SoC variant and register the clock accordingly. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Michael Trimarchi <[email protected]> Reviewed-by: Peng Fan <[email protected]>
2025-03-17clk/stub: add sc7280-rpmh clockCaleb Connolly
Stub the RPMh clock controller on SC7280 Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: sc7280: add GENI, PCIe, and more USB clocksCaleb Connolly
Add support for a bunch of new clocks, including PCIe, GENI (for all peripherals used on the RB3 Gen 2), and some missing USB clocks. Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: sc7280: add some debug dataCaleb Connolly
Dump a few PCIe and USB clocks Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: bubble up qcom_gate_clk_en() errorsCaleb Connolly
If we try to enable a gate clock that doesn't exist, we used to just fail silently. This may make sense for early bringup of some core peripherals that we know are already enabled, but it only makes debugging missing clocks more difficult. Bubble up errors now that qcom_gate_clk_en() can return an error code to catch any still-missing clocks and make it easier to find missing ones as more complicated peripherals are enabled. Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: apq8016: improve clk_enable loggingSam Day
Properly warn when an unknown clock is enabled. Signed-off-by: Sam Day <[email protected]> Reviewed-by: Caleb Connolly <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: apq8016: add PRNG_AHB_CLKSam Day
This clock needs to be enabled for the msm-rng driver to work on MSM8916, otherwise accessing the PRNG register block causes a data abort. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Sam Day <[email protected]> Reviewed-by: Caleb Connolly <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: apq8016: use BIT macro for clk en_valsSam Day
This reads a little bit nicer (IMO), and is consistent with the kernel. Signed-off-by: Sam Day <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Caleb Connolly <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-17clk/qcom: add initial clock driver for ipq9574Varadarajan Narayanan
Add initial set of clocks and resets for enabling U-Boot on ipq9574 based RDP platforms. Reviewed-by: Caleb Connolly <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Caleb Connolly <[email protected]>
2025-03-11clk: rzg2l: Ignore disable for core clocksPaul Barker
Following on from commit 9a699a0a0d62 ("clk: rzg2l: Ignore enable for core clocks"), we also need to ignore attempts to disable core clocks to avoid the need for conditionals around clk_disable_bulk() calls in drivers which support both RZ/G2L and other Renesas SoCs. Signed-off-by: Paul Barker <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2025-03-10Merge tag 'v2025.04-rc4' into nextTom Rini
This uses Heinrich's merge of lib/efi_loader/efi_net.c which results in no changes.
2025-03-03clk: versal: Store driver data in data sectionPadmarao Begari
Line 171 in README is describing that before relocation no code should use global variable because global variables are placed to BSS section which is initialized to 0 after relocation. On Versal platforms clock driver is initialized before relocation (via using dm,bootph-all flag in DT) and global variables are initialized which works if this is used only before relocation. But the variables are used after relocation too but values are zeroed which is ending up incorrect behavior. That's why place variables to data section to ensure that values are not cleared which is for now the quickest temporary solution. The correct way to do it is to move all global variables to private data to avoid it. Signed-off-by: Padmarao Begari <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2025-03-03clk: versal: Update the reference clocks as per bindingsVenkatesh Yadav Abbarapu
As per the bindings the reference clocks naming has changed from "pl_alt_ref_clk" to "pl_alt_ref" and "ref_clk" to "ref". Update the same in the clock driver. Also add the fallback option for older DT bindings. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2025-02-28clk: rockchip: Correct usage of IS_ENABLED() macroTom Rini
These two files were using IS_ENABLED() to test for CONFIG flags but omitted the CONFIG_ prefix and so did not work as expected. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2025-02-26clk: stub: add sm8150 compatible idJulius Lehmann
Add support for sm8150 clock controller to clk stub driver. Signed-off-by: Julius Lehmann <[email protected]> Reviewed-by: Neil Armstrong <[email protected]>
2025-02-26clk: add stub clock driverCaleb Connolly
Add a stub clock driver which can be used to bind clock controllers which aren't required for the platform to boot, but which are needed for U-Boot drivers to work. In addition, add a NOP parent driver to allow for binding the parent nodes of the clock. Initially this driver supports a Qualcomm platform where the MMC driver tries to fetch the RPM clock controller, which is not actually required for the device to work. Reviewed-by: Neil Armstrong <[email protected]> Acked-by: Ilias Apalodimas <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2025-02-25Merge tag 'u-boot-socfpga-next-20250225' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816 Please pull the SoCFPGA changes for next from u-boot-socfpga, containing boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The changes include: 1. Board-specific configurations and setup required to enable Agilex 5 operation in U-Boot. 2. Integration of cache coherency unit (CCU) initialization routine, including CCU conguration in DT. 3. Clock, firewall (configured in DT), SMMU, low level initialization specific to Agilex 5. 4. Integration of memory initialization routine, including DDR setup. This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
2025-02-25drivers: clk: agilex5: Set PLL to asynchronous modeAlif Zakuan Yuslaimi
PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition. To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver. Signed-off-by: Muhammad Hazim Izzat Zamri <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25drivers: clk: agilex5: Replace status polling with wait_for_bit_le32()Alif Zakuan Yuslaimi
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function which supports accurate timeout. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>