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Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Explicitly set the CLK_PARENT_XTAL flag for fixed factor clocks.
Prior to this, it was assumed that clock ID 0 was CLK_XTAL and other
IDs used a different clock tree when no parent was explicitly set.
Making the parent explicit will allow us to remove this confusing
behavior in the future.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-8-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Move repeated *_PARENT() macros from chip-specific .c files to the
common mtk-clk.h file.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-4-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add new MUX_GATE_MIXED and MUX_GATE_MIXED_FLAGS macros for mixed parent
muxes that have a gate. These will be used in a few drivers where we
already have this type of mux clocks.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-3-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Rename CLK_DOMAIN_SCPSYS to CLK_MUX_DOMAIN_SCPSYS to make it more clear
that this flag only applies to MUX clocks and not other clock types.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-2-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-1-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add new clock driver for MedaiTek MT8189 and compatible SoCs.
Signed-off-by: Chris Chen <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as
MUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member
of the union instead of parent.
This will be needed by the incoming mt8189 clock driver.
Reviewed-by: Julien Stephan <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add support for external clock parent type in MediaTek clock driver to
allow multiple external clock sources.
This is intended to eventually replace CLK_PARENT_XTAL which only allows
a single external clock source. Replacing CLK_PARENT_XTAL is not trivial
since it would required touching all chip-specific drivers. So that is
saved for another day.
Before this change, the only way to add additional external clocks was
to use a clock ID mapping and add the external clock in the fixed clocks
portion of the CLK_PARENT_TOPCKGEN clocks. After this change, such hacks
are no longer necessary and external clocks can be added in a cleaner
way.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add helper functions to check if a clock ID corresponds to a particular
clock type (mux, gate, fdiv). This simplifies the code and makes it more
readable.
Additionally, it removes the restriction that fdivs_offs < muxes_offs <
gates_offs by making the checking more strict in some places. This will
allow future drivers to not have to define a mapping to meet this
requirement.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Refactor duplicate parent rate lookup code into a common function.
Instead of relying on rules like X is always the parent of Y, we use
the driver ops pointer to make sure we are actually getting the correct
parent clock device. This allows the same function to be called from
different clock types and will allow future chip-specific clock drivers
to not have to follow the rules as strictly.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Fix the private data type struct type in a couple of infrasys clock
functions.
struct mtk_cg_priv is a superset of struct mtk_clk_priv and has the same
layout at the beginning so there was no compile errors or runtime bugs.
This could only be found by inspecting the code.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.
Fixes: 5e9bbbdab003 ("clk: mediatek: mt8188: add missing fixed clock")
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Reviewed-by: Julien Stephan <[email protected]>
Tested-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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The MT7622 infracfg and pericfg drivers both use
mtk_common_clk_infrasys_init() for probe, which populates struct
mtk_clk_priv and stores gate definitions in the clk_tree. However,
both drivers were incorrectly wired to mtk_clk_gate_ops which expects
struct mtk_cg_priv with separately populated gates/num_gates/gates_offs
fields from mtk_common_clk_gate_init().
Since those fields were never set, any attempt to enable an infracfg or
pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL.
Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match
the init function.
Fixes: 72ab603b201 ("clk: mediatek: add driver for MT7622")
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: David Lechner <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452
- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes
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Add clock driver for RK3506.
Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Prepare v2026.04-rc4
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After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
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This is required for the IPUv3 driver to migrate to CCF, changes are
largely based on the Linux kernel equivalent.
Add new gate2_flags function (also present in the Linux code) to set
required flags.
Add usboh clock to get rid of error.
Signed-off-by: Brian Ruley <[email protected]>
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Reduces the number of checkpatch warnings in the following commits.
Signed-off-by: Brian Ruley <[email protected]>
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Add clock driver support for STM32MP21 SoCs.
Signed-off-by: Nicolas Le Bayon <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Prepare v2026.04-rc3
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Julien Stephan <[email protected]> says:
This series adds basic support for Mediatek soc MT8195:
- clock driver
- watchdog
- add a new macro helper to define gate clock. Other driver can be
cleaned later to use the new macro
Other driver will be added later.
It will also serve as basis for board support such as MT8395_EVK based
on MT8195.
Link: https://lore.kernel.org/r/[email protected]
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The following clocks have been added for MT8195 SoC:
apmixedsys, topckgen, infracfg
These clocks driver are based on the ones present in the kernel:
drivers/clk/mediatek/clk-mt8195-*
Signed-off-by: Chris-QJ Chen <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
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Add helper macro for mtk_gate, the same way, there are macros for
FIXED_CLK, MUX and FACTOR.
Signed-off-by: Julien Stephan <[email protected]>
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Julien Stephan <[email protected]> says:
I recently submitted the clock driver for MT8188. I naively submitted a
driver that was ported from the kernel driver, and mostly work to boot a
kernel.
Recently David Lechner, added support for the clk dump command for
Mediatek clock drivers, so I used it to check the MT8188 and found
several issues fixed on this series:
- removed topckgen_cg, gates are now part of topckgen
- fixed several parents clocks
- added missing fixed clocks
While at it, I also refactored a bit the driver to improve readability,
and future additions to it.
Link: https://lore.kernel.org/r/[email protected]
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Refactor some part of the driver to improve readability and future
additions:
- use CLK_TOP_NR_CLK for added clocks
- rename the id map to make it more clear that the map applies to top
clocks only
- refactor the id map to improve readability
- xtal2_rate is only used for PLL clocks, so only the apmixedsys clock
tree needs it. Remove it elsewhere.
Signed-off-by: Julien Stephan <[email protected]>
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Fix a number of clock parent definitions for MT8188 clocks.
Signed-off-by: Julien Stephan <[email protected]>
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CLK_TOP_CLK13M was missing, add it.
Signed-off-by: Julien Stephan <[email protected]>
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FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 3)
--> CLK_TOP_APLL1_D4 declares CLK_TOP_APLL1 as it's parents
MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7)
--> CLK_TOP_APLL1 declares apll1_parents as it's parents
static const int apll1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_APLL1_D4
};
--> CLK_TOP_APLL1_D4 is a parent of CLK_TOP_APLL1
Fix this, by correctly setting CLK_TOP_APLL1_DX parent to CLK_APMIXED_APLLX
Signed-off-by: Julien Stephan <[email protected]>
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Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space.
Commit 8aeeeff50d46 ("clk: mediatek: allow gates in topckgen drivers")
added support for gates in topckgen driver.
This commit fixes MT8188 driver, the same way commit ba207d7f54f9 ("clk:
mediatek: mt8365: remove separate topckgen-cg driver") does for MT8365.
Signed-off-by: Julien Stephan <[email protected]>
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Peng Fan (OSS) <[email protected]> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf
CI: https://github.com/u-boot/u-boot/pull/865
Link: https://lore.kernel.org/r/[email protected]
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Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <[email protected]> #TI boards
Acked-by: Yao Zi <[email protected]> #TH1520
Signed-off-by: Peng Fan <[email protected]>
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TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
# Conflicts:
# drivers/ddr/altera/Makefile
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operations
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In v2025.10, the Agilex clock driver was updated to support
clk_enable() and clk_disable() using clock-ID based bitmasks.
However, only AGILEX_NAND_CLK was implemented, while the NAND DT
node still referenced both nand and nand_x clocks.
Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
clock-ID specification, clk_enable() failed during NAND probe.
As a result, the Denali NAND controller never completed
initialization.
Fix this by mapping the NAND X clock to the existing l4_mp clock
bitmask, aligning the DT expectations with the clock driver and
restoring proper NAND controller initialization.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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When built without CONFIG_CMD_CLK, we get a warning about the unused
clk_names variable:
../drivers/clk/clk_zynqmp.c:153:27: warning: ‘clk_names’ defined but not used [-Wunused-const-variable=]
153 | static const char * const clk_names[clk_max] = {
So also guard it with CONFIG_CMD_CLK to get rid of that.
Signed-off-by: Peter Korsgaard <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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It looks like the original zynqmp typo was copied to versal as well. Fix
both.
Signed-off-by: Peter Korsgaard <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add MBUS Master Clock Gating Register for H6 and H616
For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.
The bit locations are from H6/H616 User Manuals.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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During clock's registration, clock's name are used to establish parent -
child relation. On STM32MP13 and STM32MP25, most of SCMI clocks are parent
clocks.
Since commit fdb1bffe2827 ("clk: scmi: Postpone clock name resolution"),
all scmi clocks are named by default "scmi-%zu" until they are enabled,
it breaks clocks registration and boot process for STM32MP13/25
platforms.
Rework the STM32 core clock driver and STM32MP13/25 clock description
to use clock index instead of their real name.
Introduce struct clk_parent_data which allows to identify parent clock
either by index or by name. Name is only used for particular clocks
provided by IP which are clock provider as i2s/i2s_ckin, usb0/ck_usbo_48m,
and ltdc/ck_ker_ltdc.
STM32_GATE() and STM32_COMPOSITE_NOMUX macros are updated in order to
use parent clock index.
As STM32MP13 supports both SPL and SCMI boot, keep using an array
with clock's name for SPL.
Fixes: fdb1bffe2827 ("clk: scmi: Postpone clock name resolution")
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
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Reorder include following rules available here :
https://docs.u-boot.org/en/latest/develop/codingstyle.html#include-files
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
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Replace casting with long to IS_ERR_VALUE() macro to check for error
return values from rate calculation functions. This is the recommended
way to check the return value from clock rate functions.
Signed-off-by: David Lechner <[email protected]>
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Pass the unmapped parent ID when setting parent for mux clocks.
For technical reasons, some Mediatek clock driver have a mapping between
the clock IDs used in the devicetree and ID used in the generic clock
framework.
The mtk_clk_mux_set_parent() function is comparing the passed mapped
parent ID against the unmapped IDs in the chip-specific data structures.
Before this change, we were passing the mapped parent ID. When there is
a mapping, this resulted in buggy behavior (usually just incorrectly
failing to find a match and returning an error). We need to pass the
unmapped ID of the parent clock instead for the matching to work
correctly.
Since the reverse lookup is a bit verbose, a helper function is added to
keep the code clean.
Fixes: b1358915728b ("clk: mediatek: add of_xlate ops")
Signed-off-by: David Lechner <[email protected]>
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David Lechner <[email protected]> says:
I needed to debug some clock issues and found some places where pointer
addresses were being printed when names were available. The addresses
are not very helpful, but the names are. So here a couple of patches to
improve that.
Link: https://lore.kernel.org/r/[email protected]
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Consistently use the device name in debug messages. The clk-uclass file
previously had a mix of printing the dev pointer and the device name.
Changing all to use the device name makes the debug messages more
useful.
Signed-off-by: David Lechner <[email protected]>
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Change the format specifier from %p to %s when printing the ofnode name
so that the actual name is printed instead of the pointer address.
Signed-off-by: David Lechner <[email protected]>
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Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
[casey: indentation fix]
Signed-off-by: Casey Connolly <[email protected]>
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Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
Signed-off-by: Swathi Tamilselvan <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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