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Consistently use the device name in debug messages. The clk-uclass file
previously had a mix of printing the dev pointer and the device name.
Changing all to use the device name makes the debug messages more
useful.
Signed-off-by: David Lechner <[email protected]>
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Change the format specifier from %p to %s when printing the ofnode name
so that the actual name is printed instead of the pointer address.
Signed-off-by: David Lechner <[email protected]>
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Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
[casey: indentation fix]
Signed-off-by: Casey Connolly <[email protected]>
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Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
Signed-off-by: Swathi Tamilselvan <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Suggested-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <[email protected]>
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Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <[email protected]>
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Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <[email protected]>
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Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <[email protected]>
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Fix a number of clock parent definitions for MT8365 clocks. Most of
these are just informational or don't make a function change.
The clocks with the new PLL_FACTOR2 macro and the change in apu_parents
are fixing actual bugs.
Signed-off-by: David Lechner <[email protected]>
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Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <[email protected]>
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Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <[email protected]>
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Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <[email protected]>
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David Lechner <[email protected]> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
Link: https://lore.kernel.org/r/[email protected]
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Implement dump callbacks for Mediatek clocks. On these platforms, there
are 100s of clocks, so it can be easy to miss mistakes. The dump
callbacks will be useful for debugging and verifying clock configs.
Signed-off-by: David Lechner <[email protected]>
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Add range initializers to the id_offs_map arrays in the mt7623 clk
driver to set unmapped IDs to -1. This prevents accidental usage of
unmapped IDs that would otherwise map to 0.
mtk_common_clk_of_xlate() checks these values for < 0 and returns
-ENOENT in that case.
A range initializer covering the entire array is used since it is less
error-prone than manually looking up the value of each macro in the
existing initializers and checking for gaps. It is placed first so that
the specific initializers override it.
Signed-off-by: David Lechner <[email protected]>
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Update documentation comments to clarify the difference between which
.id fields are mapped (only struct clk.id) vs. unmapped (all struct
mtk_*.id and .parent fields). The unmapped IDs are the ones defined
in the devicetree bindings, while the mapped IDs are the ones used as
the index into the various clk arrays.
Also fix spelling of "parent" while we are touching this.
Signed-off-by: David Lechner <[email protected]>
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Add driver-specific of_xlate ops for MediaTek clocks. This provides
better checking of the args passed from the devicetree. Compared to
the default of_xlate implementation, this will return -EINVAL if there
are zero args (id is always required) and -ENOENT if the id is out of
range for the clock type. This will protect against out of bounds array
accesses later on when the clk->id is used to index into the clock
data arrays.
If there is a id_offs_map, then we have to do that translation first
before checking the id to see if it is in range. There is no sense in
doing the mapping multiple times, so we save the mapped ID in clk->id
and remove mtk_clk_get_id().
mtk_clk_find_parent_rate() also had to be updated since it creates a
temporary struct clk to represent the parent clock. It now has do the
translation in case the parent clock also uses an id_offs_map.
Signed-off-by: David Lechner <[email protected]>
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Move all infrasys ops and related functions next to each other in the
file for better organization.
Generally all ops functions are grouped together like this for the other
ops types (apmixedsys, topckgen, etc). However the infrasys functions
were mixed in with the other sections making them harder to find. This
will also give a logical place to add any future infrasys-specific
functions.
Signed-off-by: David Lechner <[email protected]>
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Add id_offs_map_size field to struct mtk_clk_tree and populate it for
all existing drivers.
Currently, there is no bounds checking when accessing the id_offs_map
array. Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <[email protected]>
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Add num_gates field to struct mtk_cg_priv and populate it for all
existing drivers.
Currently, there is no bounds checking when accessing the gates array.
Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <[email protected]>
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Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to
the mtk_clk_tree struct and populate them in the clk trees for all
existing drivers.
Currently, there is no bounds checking when accessing the arrays in
the clk tree structs. Adding these fields will allow for bounds checking
in the future.
Signed-off-by: David Lechner <[email protected]>
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Tom Rini <[email protected]> says:
As seen by a number of patches fixing memory leaks, U-Boot has a problem
with developer expectations around devm_kmalloc and friends. Namely,
whereas in Linux these memory allocations will be freed automatically in
most cases, in U-Boot this is only true if DEVRES is enabled. Now,
intentionally, in xPL phases, we do not (and do not offer as an option)
enabling DEVRES. However in full U-Boot this is left either to the user,
or some drivers have select'd DEVRES on their own. This inconsistency is
a problem. This series goes and deals with two small issues that were
shown by having all drivers that use devm_.alloc to allocate memory also
select DEVRES and then we make DEVRES no longer be a prompted option and
instead select'd as needed. We do not make this unconditional as it
would result in growing the resulting binary on the many platforms which
have no users of the devm_.alloc family of functions.
Link: https://lore.kernel.org/r/[email protected]
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove the CLOCK_* aliases of the CLOCK_PARENT_* macros. One name for
each flag is sufficient.
Signed-off-by: David Lechner <[email protected]>
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Julien Stephan <[email protected]> says:
The MediaTek MT8188 is a ARM64-based SoC with a dual-core Cortex-A78
cluster and a six-core Cortex-A55 cluster. It includes UART, SPI,
USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and
several LPDDR3 and LPDDR4 options.
This series adds basic support for MT8188.
Link: https://lore.kernel.org/r/[email protected]
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The following clocks have been added for MT8188 SoC:
apmixedsys, topckgen, infracfg, pericfg and imp_iic_wrap
These clocks driver are based on the ones present in the kernel:
drivers/clk/mediatek/clk-mt8188-*
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
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scmi_generic_protocol_version() request is done twice in scmi_clk_probe().
Remove first call which is useless.
Fixes: ae7e0330ce22 ("clk: scmi: add compatibility with clock protocol 2.0")
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In scmi_clk_probe(), in case of CLK_CCF is not enabled, parent private
data is not set, so in scmi_clk_gate(), an uninitialized priv struct is
retrieved.
SCMI request is performed either using scmi_clk_state_in_v1 or
scmi_clk_state_in_v2 struct depending of the unpredictable value of
priv->version which leads to error during SCMI clock enable.
Issue detected on STM32MP157C-DK2 board using the SCMI device tree
stm32mp157c-dk2-scmi.dts.
Fixes: 0619cb32030b ("firmware: scmi: Add clock v3.2 CONFIG_SET support")
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Fix typo attibute, rename scmi_clk_get_attibute() to
scmi_clk_get_attribute().
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Change mt8365_evk_defconfig to use CONFIG_OF_UPSTREAM=y and delete the
U-Boot copy of the devicetree source files for mt8365.
The upstream devicetree is identical to the U-Boot one being removed
(other than having more nodes for devices not used by U-Boot and
upstream fixed a compatible string in &scpsys, also not affecting
U-Boot).
There was one minor glitch with upstream missing a few topckgen macro
definitions, so those are added to the clock driver directly as a
workaround.
Reviewed-by: Macpaul Lin <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Later versions of the datasheet makes it clear D3 do not have any
realtime module stop control registers (RMSTPCRx). Remove the
manipulation of them from the module clock table to match this.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Niklas Söderlund <[email protected]>
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Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
last before booting OS") enabling the module gated by bit 8 in MSTP4
prevents Linux from booting. The bits 8 and 7 of MSTP4 where only
documented in early versions of the datasheet and have since been
removed.
To allow Linux to boot update the MSTP4 enable value to reflect the
hardware default, 0x80.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Niklas Söderlund <[email protected]>
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If CONFIG_OF_PLATDATA=y , then the udevice has no valid OF node associated
with it and ofnode_valid(node) evaluates to 0. The dev_read_u32_default()
call ultimately reaches ofnode_read_u32_index() which invokes fdt_getprop()
and passes result of ofnode_to_offset(node) as an offset parameter into it.
The ofnode_to_offset(node) returns -1 for invalid node, which leads to an
fdt_getprop(..., -1, ...) invocation, which will crash sandbox with SIGSEGV
because libfdt can not handle negative node offsets without full tree check,
which U-Boot inhibits to keep size lower.
Add dev_has_ofnode(dev) check and do not assign clock rate in case the
device has no valid node associated with it, and do not call any of the
dev_read_*() functions for devices without valid nodes.
Signed-off-by: Marek Vasut <[email protected]>
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Versal Gen 2 is using enhancement SMC format but in near future SCMI client
should be used. This patch is just bridging this gap till SCMI server is
fully tested.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com
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Remove unneeded debug messages, parenthesis and fix error message.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com
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When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock
identifier in clk uclass that's why it is necessary to mask lower bits
which are clock ID.
Also check that ID not bigger then maximum supported clock.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com
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The commit 1b267fe1824e ("firmware: xilinx: Prepare code for new SMC
firmware format") introduce new __data macro that's why use it in clock
driver too.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/eac8d0ab60a018d6c59aa28c49691839a3eec174.1762511327.git.michal.simek@amd.com
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776
Highlights:
*
SPL / MMC:
o
Fix Kconfig handling for
SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
o
Correct raw sector calculations and respect explicit sector values
when loading U-Boot from MMC in SPL
o
Adjust raw MMC loading logic for SoCFPGA platforms
*
EFI boot:
o
Permit EFI booting on SoCFPGA platforms
o
Disable mkeficapsule tool build for Arria 10 where unsupported
*
Agilex5:
o
Upgrade SDHCI controller from SD4HC to SD6HC
o
Enable MMC and Cadence SDHCI support in defconfig
o
Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
o
Revert incorrect GPIO configuration for SDIO_SEL
o
Refine U-Boot DT handling for SD and eMMC boot variants
*
SPI:
o
Allow disabling the DesignWare SPI driver in SPL via Kconfig
*
Board / configuration fixes:
o
Enable random MAC address generation for Cyclone V
o
Fix DE0-Nano-SoC boot configuration
o
Remove obsolete or conflicting options from multiple legacy
SoCFPGA defconfigs
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Remove duplicate '@parent' field documentation in struct mtk_composite.
There is no need to say the same thing twice.
Also fix spelling mistake in the word "parent" while we're at it.
Signed-off-by: David Lechner <[email protected]>
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Markus Schneider-Pargmann (TI.com) <[email protected]> says:
This series cleans up the direct dependency of ARCH_OMAP2PLUS to compile
ti/clk.c which holds common functions for other clock drivers. It creates its
own config symbols for these common functions and for the omap-cm driver as
well.
The omap-cm driver config symbol is added as default enabled.
Link: https://lore.kernel.org/r/20251128-topic-am33-clk-regmap-dep-v2026-01-v2-0-451b4f4e7e85@baylibre.com/
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Add a Kconfig symbol for this stub driver to avoid clock dependencies on
an architecture symbol. Enable it by default.
Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Create a new symbol for the common clock functions used by some of the
omap2plus clock drivers. These drivers now select this new symbol when
they need the functions. Note these common functions are not
ARCH_OMAP2PLUS specific.
Note that the common functions are using regmap, so select it here.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
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While this change was intended to fix a mistake in the code, of calling
the ERR_PTR macro but not making use of the result, it seems that
functionally platforms depend on the loop not existing here. The TI K3
families of platforms for example were broken by this commit.
This reverts commit fe780310cfa8bf5a093894b5cd7fe85c6b02fd91.
Reported-by: Nishanth Menon <[email protected]>
Reviewed-by: Andrew Goodbody <[email protected]>
Reviewed-by: Nishanth Menon <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2026.01-rc4
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Andrew Goodbody <[email protected]> says:
Smatch reported an error where a value calculated by ERR_PTR was not
used. Fixing this to return the generated value led to a test failure
which meant updating the sandbox clock code so that it would still cause
the tests to pass with the above correction.
Debugging this problem led to a SIGSEGV which is addressed in 1/3.
Possible memory leaks noticed are addressed in 3/3.
Link: https://lore.kernel.org/r/[email protected]
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In clk_set_default_rates() memory is allocated to store the clock rates
that are read. Direct returns fail to free this memory leading to a
memory leak so instead use 'goto fail;' which will then perform the free
before exiting the function.
Signed-off-by: Andrew Goodbody <[email protected]>
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In clk_set_default_get_by_id ret is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
Then fixup the sandbox code so that the test dm_test_clk does not fail
as it relied on the broken behaviour.
Finally disable part of the test that does not work correctly with
CLK_AUTO_ID
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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