| Age | Commit message (Collapse) | Author |
|---|
|
Isolate Renesas R-Car Gen3 clock driver to R-Car Gen3 and Gen4 and RZ/G2L.
The Renesas R-Car Gen5 uses SCMI clock protocol driver instead. This is
a preparatory change for R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/28119
- New Boards support:
rk3588: MNT Reform2
rk3528: Radxa ROCK 2A/2F
rk3576: ArmSoM Sige1, Luckfox Omni3576, FriendlyElec NanoPi M5,
Radxa ROCK 4D
rk3568: Lunzn FastRhino R66S
- Other board level updates.
|
|
Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Allow us to power up UART7 so we can load the QUP firmware, this is used
for bluetooth on RB3 Gen 2 and possibly other boards.
Additionally add the UART5 clocks so we can adjust baud rate for UART
Signed-off-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Stub the RPMh clock controller on SC7180.
Signed-off-by: Jens Reidel <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add a clock driver for the SM7150 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Danila Tikhonov <[email protected]>
Co-developed-by: Jens Reidel <[email protected]>
Signed-off-by: Jens Reidel <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Stub the RPMh clock controller on SM6350.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
|
|
Add Clock driver for the GCC block found in the SM6350 SoC.
Reviewed-by: Casey Connolly <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
|
|
Clean up some defines which are not used in the driver.
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
The global clock controller on SDM670 is similar to SDM845, so let's add
support here.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: David Wronek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Necessary for MMC to successfully probe all clocks.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: David Wronek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
This reverts commit 644b4650ee57c429bede77f44752cc867dac0e00.
While the intention of the above commit is correct, it leads to test
failures in CI that need to be addressed at the same time.
Signed-off-by: Tom Rini <[email protected]>
|
|
A few clock drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
|
|
In clk_set_default_get_by_id ret is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Acked-by: Quentin Schulz <[email protected]>
|
|
Andrew Goodbody <[email protected]> says:
Should return value calculated by ERR_PTR as calling code attempts to
check for it.
Also do not dereference a pointer that could be an error pointer before
checking it with IS_ERR.
Link: https://lore.kernel.org/r/[email protected]
|
|
In versaclock_probe vc5->pin_xin may be an error pointer so need to
check with IS_ERR before attempting to dereference it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
In versaclock_get_name -ENOMEM is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure
Signed-off-by: Manikandan Muralidharan <[email protected]>
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.
Signed-off-by: Manikandan Muralidharan <[email protected]>
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
The cv1800b_clk_setfield function returns void, but was doing "return
writel(...);" and while seemingly having a void function return a void
function is not a warning, when readl is a macro this problem is shown.
Correct the code to instead simply call writel.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Yao Zi <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2
zynqmp:
- DT updates
- Enable new commands
mbv:
- Simplify defconfigs
clk:
- Separate legacy handler and use SMC handler
misc:
- Tighten TTC Kconfig dependency
net:
- Add 10GBE support to Gem
pwm:
- cadence-ttc: Fix array sizes
fwu:
- Add platform hook support
spi:
- Remove undocumented cdns,is-dma property
video:
- Fix DPSUB RGB handling
|
|
Peng Fan (OSS) <[email protected]> says:
Misc update on firmware scmi:
- Typo fix
- Use io helpers
- Use PAGE_SIZE for arm64
- Add IN_USE error code
- Add more error info
- Support scmi max rx timeout in mailbox
- Add myself as scmi maintainer, AKASHI contributed most code, but
seems he is not invovled in the developement anymore, I volunteer to
help here.
Some items on list that I am thinking to add:
- align with linux kernel to use cpu_to_le32 and le32_to_cpu, but have not find
a good way to use the helpers.
- Add SCMI version negotiation as Linux Kernel
Link: https://lore.kernel.org/r/[email protected]
|
|
Use dev_dbg to dump device name, dev_dbg also a encapsulation call
to log() and print(). So it is ok to use dev_dbg.
Signed-off-by: Peng Fan <[email protected]>
|
|
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.
The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.
Signed-off-by: Naman Trivedi <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Acked-by: Senthil Nathan Thangaraj <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
|
|
It is a preparation for adding enhacement format support that's why there
is a need to separate current support to own function.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c4d546553d4f0d69ef75fb1132b7121f36dd306c.1756388537.git.michal.simek@amd.com
|
|
There is no reason to call SMC from clock driver directly when clock driver
is a child of firmware driver which is providing it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/d383d5fea680b33d2eddbca108c452cee97e98ea.1756388537.git.michal.simek@amd.com
|
|
Merge the outstanding changes from the 'next' branch to master.
|
|
Add "in SPL" to the SPL related driver help texts.
Signed-off-by: Yegor Yefremov <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* DDR updates:
- IOSSM mailbox compatibility check
- Correct DDR calibration status handling
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
|
|
A second return following the first return is unreachable code so remove
it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
|
|
FIELD_GET() macro is used during EMAC clock source selection
for better code readability and maintainability.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Fix the incorrect bit masking and bit shift used to compute EMAC
control which in turn is used to select EMAC clock from EMAC
source A or B.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Update Agilex clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.
The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the Agilex clock
manager peripheral PLL register based on the given clock ID.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Prepare v2025.10-rc5
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27684
- Add i.MX8 ahab-commit command.
- Add support for flashing board with UUU on imx93_frdm.
- Fix the acces of PFUZE100 regulator desc.
- Add more i.MX6 PWM clock definitions.
- Enable OP-TEE on phytec-imx8m and update documentation.
- Enable PCI host controller on iMX95 19x19 EVK.
[trini: Fixup spacing issues]
Signed-off-by: Tom Rini <[email protected]>
|
|
Following the work done in commit 7f39ad5a ("clk: imx6q: Add definition
for IMX6QDL_CLK_PWM1"), this commit adds definitions for PWM2, PWM3, and
PWM4 clocks. Allowing one to use these PWM modules together with DM_CLK.
Note that the solution was verified only against PWM3.
Signed-off-by: Ricardo Simoes <[email protected]>
Signed-off-by: Mark Jonas <[email protected]>
|
|
clk_set_rate returns the actual clock rate, When assigned clock rate is
higher than 0x7FFFFFFF, the return value will be recognized as error.
Change to IS_ERR_VALUE to check the return value.
Signed-off-by: Ye Li <[email protected]>
|
|
Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX
blkctrl and LVDS blkctrl.
Since multiple blkctrl device for different blkctrl may be enabled,
and each has dedicated clock id from 0. We must enable CLK_AUTO_ID
to avoid conflict on clock id.
Signed-off-by: Ye Li <[email protected]>
|
|
into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27673
- Switch to upstream devicetree for TH1520 platform
- Remove fdt_high env variable
- Support SMP on RISC-V cores with Zalrsc only
- Make MPFS Generic
- riscv: dts: starfive: prune redundant jh7110-common
|
|
It's common that UARTs are bound and probed before U-Boot relocation,
in which case the clocks of UART and UART's pincontroller must be
registered first. Let's apply DM_FLAG_PRE_RELOC to the driver, allowing
it to bind before relocation.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
Replace RIFSC check access APIs by grant/release access ones that handle
the RIF semaphores.
Signed-off-by: Gatien Chevallier <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
|
|
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
Prepare v2025.10-rc4
|
|
- Fix issues reported by smatch
- exynos4210-origen cleanups
- e850-96 improvements
|
|
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2025.10 cycle:
This set includes smatch fixes for clocks and mmc and one QSPI fix.
|
|
Operations are not changing that's why mark them as const which ensure that
structure will be moved from .data section to .rodata section.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/92eb9e90189d8b96246966633478662076da7185.1753444878.git.michal.simek@amd.com
|
|
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
