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GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:
- SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
Should be 0x42018, this is an invalid register close to the USB clocks.
- SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
Should be 0x43018, this is the SDCC1 clock.
When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.
This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.
Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.
Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family")
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add i.MX6UL clk driver for i.MX6UL CLK driver model usage
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Christoph Niedermaier <[email protected]>
Tested-by: Christoph Niedermaier <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Prepare v2025.07-rc3
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Starting from commit ac30d90f336 (clk: Ensure the parent clocks are enabled
while reparenting), MediaTek filogic platforms will crash on booting when
initializing mmc devices.
The root cause is that to simplify the code, we reused the topckgen ops for
apmixedsys clocks as they share the get_rate with topckgen clocks while the
clk enable/disable ops are not available for apmixedsys clocks.
Now that a clock will be enabled first before reparenting, we have to add
dummy enable/disable ops for apmixedsys to avoid unexpected behavior when
apmixedsys clocks are the parent clock of the to-be-reparenting clocks.
Fixes: 40746bf429d (clk: mediatek: add clock driver support for MediaTek MT7981 SoC)
Fixes: 37d5a9a29dc (clk: mediatek: add clock driver support for MediaTek MT7986 SoC)
Fixes: ece4e5804f5 (clk: mediatek: add clock driver support for MediaTek MT7987 SoC)
Fixes: 421436981a2 (clk: mediatek: add clock driver support for MediaTek MT7988 SoC)
Signed-off-by: Sam Shih <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
with only output clocks for external sensors, which are barely useful in
bootloaders, removed.
Same as the mainline driver, it currently lacks of ability to enable and
reconfigure PLLs, which could be implemented later.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add the device specific driver data, and the clock configuration.
Signed-off-by: Jonathan Currier <[email protected]>
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The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled
while reparenting") add a call to clk_enable() for the parent clock.
For clock drivers that do not implement the enable() ops, like most
Rockchip clock drivers, this now cause the set_parent() ops to never
be called when CLK_CCF=n (default for Rockchip).
clk_enable() typically return -ENOSYS when the enable() ops is not
implemented by the clock driver, with CLK_CCF=y clk_enable() instead
return 0 when the enable() ops is unimplemented.
Change to ignore -ENOSYS from the newly introduced clk_enable() call to
fix this regression and restore the old behavior of set_parent() ops
being called regardless of if enable() ops is implemented or not.
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Dang Huynh <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
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Clock driver based on SCMI clock management protocol in Linux checks
clock state, parent and rate control permissions. To be consistent with
the kernel driver, add this check here. CLOCK_GET_PERMISSIONS is from
ARM System Control and Management Interface Platform Design Document 3.2.
When using common clock framework (CCF), use the clock signal ID to get
the clock registered by clk_register() in scmi_clk_probe(), and then
obatin the struct clk_scmi variable with container_of().
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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This patch adds the command CLOCK_PARENT_SET that can be used to set the
parent of a clock. ARM SCMI Version 3.2 supports to change the parent of
a clock device.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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If there is a SoC specific SCMI protocol driver, using
scmi_proto_driver_get() function can avoid to add SoC specific code to
scmi_agent-uclass.c.
Signed-off-by: Alice Guo <[email protected]>
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Caleb Connolly <[email protected]> says:
Introduce a new event to signal that the live tree has been built,
allowing boards to perform fixups on the tree before devices are bound.
Crucially this allows for devices to be enabled or disabled, but also
allows for properties that are parsed during the bind stage to be
modified (such as dr_mode for dwc3).
With this in place, mach-snapdragon is switched over to use the event
and some hacky U-Boot specific DT overrides (which had to be undone
prior to booting an image) are removed in favour of fixing up the
livetree (which is not passed on to further boot stages).
Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard
is enabled and it now uses USB host mode in U-Boot like it's bigger
sibling the RB2.
Link: https://lore.kernel.org/r/[email protected]
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The device name is always clk_qcom... Not very useful.
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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It's currently possible to make the bootloader crash on calling
clk_set_rate caused by the loop in clk_clean_rate_cache.
The loop assume that every child of the clock node are also clock
device but this is not always the case. For example it's common for a
clock to bind to a reset device or also expose a syscon if the clock
register map is also used to apply special configuration.
In such case, on accessing a device as a clock, the bootloader crash. To
correctly handle this, check if the child device is actually a clock and
ignore otherwise.
Fixes: 6b7fd3128f71 ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25974
- Fix power-domain ref counting regression.
- Fix i.MX8MP USB clock regression.
- Fix i.MX8MM osc_32k regression in SPL.
- Finish converting clock-osc-24 back to osc_24 on i.MX.
- Several imx8mp capricorn updates.
- Update Stefano Babic's email address.
- Fix fsl_qspi bug by moving AHB read buffer config after LUT.
- Fix verdin imx95 sku 0089 pid4.
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Pass the clock controller udevice into clk_register_composite(),
so it can be passed further to any registered composite clocks
and used for look up of parent clock referenced in DT "clocks"
and "clock-names" properties by phandle and name pair.
Use the clock controller udevice in imx8m_clk_mux_set_parent()
to perform accurate look up of parent clock referenced in the
CCM driver by name. If the clock name that is being looked up
matches one of the names listed in the clock controller DT node
"clock-names" array property, then the offset of the name is
looked up in the "clocks" DT property and the phandle at that
offset is resolved to the parent clock udevice. The test to
determine whether a particular driver instance registered with
clock uclass matches the parent clock is done by comparing the
OF nodes of the clock registered with clock uclass and parent
clock resolved from the phandle.
Example:
drivers/clk/imx/clk-imx8mm.c:
static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", ...
_____________|
arch/arm/dts/imx8mm.dtsi: |
clk: clock-controller@30380000 { v
clock-names = "osc_32k", "osc_24m", ...
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v
clocks = <&osc_32k>, <&osc_24m>, ...
}; _______________________|
... |
/ { v
osc_24m: clock-osc-24m {
compatible = "fixed-clock";
...
};
Signed-off-by: Marek Vasut <[email protected]>
Reported-by: Francesco Dolcini <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Tested-by: Adam Ford <[email protected]> # imx8mp-beacon
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DSI is the peripheral clock, while DSI_K is an internal kernel clock.
Even though they get the same register and same bit set to be gated,
resulting in the same behavior.
Signed-off-by: Raphael Gallais-Pou <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
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The UART clocks were added around the same time some other clock
updates were happening, so converting clock-osc-24 back to osc_24
was missed on the UART clocks for imx8mm and imx8mn, so update
them here.
Fixes: b4734c9c333b ("clk: imx: Convert clock-osc-* back to osc_*")
Signed-off-by: Adam Ford <[email protected]>
Reported-by: Christoph Niedermaier <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add clock driver support for Rockchip RK3576 SoC.
Signed-off-by: Elaine Zhang <[email protected]>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clock driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Joseph Chen <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Jiaxun Yang <[email protected]> says:
This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.
I also converted the target to OF_UPSTREAM.
This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```
Link: https://lore.kernel.org/r/[email protected]
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In upstream devicetree, clk_boston is a child of syscon node
and there is no "regmap" property for clk_boston node.
Try to check parent device first to look for syscon.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm changes for v2025.07:
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/25653
There's been a surprising amount of activity lately on the Qualcomm
side with the two oldest boards getting some fresh attention and a lot
of cleanup and polish going on across the board.
* SDM660 gets USB phy fixes and a pinctrl driver
* The recently added SA8775P/QCS9100 SoC gets a pinctrl driver
* The Qualcomm pinctrl driver now handles reserved pins correctly,
fixing crashes on some boards when running "gpio status -a"
* OF_UPSTREAM_BUILD_VENDOR is enabled in qcom_defconfig
* SDM845 and SC7280 get missing clocks added (since we're now stricter
about those). This gets USB working more reliably in more cases.
* DM_USB_GADGET is enabled for all boards using DWC3 and fasbtoot is
enabled too
* A bug in the livetree fixup code is fixed (making USB work on a lot
more platforms)
* Button label lookup is made case insensitive* bootretry becomes more dynamic, allowing it to be hijacked to make a
"persistent" boot menu that allows dropping to U-Boot shell later on
* A new qcom-phone.config fragment is added along with a phone-specific
default environment and phone-specific debugging/bringup docs. These
make U-Boot more usable on devices without a serial port or keyboard.
* The db820c gets fixed up and updated documentation
* The db410c also gets some love and modernisation as well as a new
reviewer.
* A new driver is added for the USB VBUS regulator found on various
Qualcomm PMICs
* The Qualcomm SPMI driver gets some fixes and cleanup for SPMI v5 and
v7 support.
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These are all the clocks needed to get an LCD panel working, going
through one of the LCDIF and the LDB. The media AXI and APB clocks are
also described.
Signed-off-by: Miquel Raynal <[email protected]>
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Reparenting a clock C with a new parent P means that C will only
continue clocking if P is already clocking when the mux is updated. In
case the parent is currently disabled, failures (stalls) are likely to
happen.
This is exactly what happens on i.MX8 when enabling the video
pipeline. We tell LCDIF clocks to use the VIDEO PLL as input, while the
VIDEO PLL is currently off. This all happens as part of the
assigned-clocks handling procedure, where the reparenting happens before
the enable() calls. Enabling the parents as part of the reparenting
procedure seems sane and also matches the logic applied in other parts
of the CCM.
Signed-off-by: Miquel Raynal <[email protected]>
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Add support for the resource power manager clocks over SMD/GLINK to be
stubbed.
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Select the right clock for sdhci.
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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The function should return a valid rate.
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Reviewed-by:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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These are all usually enabled, hence we don't (yet) bother configuring
their RCG src clocks.
Add them to remove the errors about missing clocks when the UFS and MMC
drivers probe.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Missing for UFS.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Necessary for UFS to successfully probe all clocks.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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These are necessary for USB gadget to come up properly, now that
qcom_gate_clk_en fails on unknown clocks.
Signed-off-by: Sam Day <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Note that this undoes the changes of commit cf6d4535cc4c ("x86:
emulation: Disable bloblist for now") as that was intended only for the
release due to time.
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Currently in j721e_init.c we check which firewalls to remove using
the board configuration (e.g CONFIG_TARGET_J721E_R5_EVM). We do this
as J721e and J7200 have different IP and firewalls but use the same
SoC definition (SOC_K3_J721E) even though they are different SoCs.
The idea was they would be similar enough that they both could use
the same SoC config to help with common code sharing. Board checks
would then be used differentiate.
This has grown far too messy to maintain any more, especially now
that there is more than one board using J721e (EVM, SK, Beagle AI64).
As differentiation is done based on board, every one of these boards
would have to have checks added for them. Instead let's split J7200
support out from J721e like how normal new SoC support is done.
This patch touches several subsystems and could not be split much better
as when we add SOC_K3_J7200 we want to make use of it in all spots that
once used the combined SOC_K3_J721E so we can turn off SOC_K3_J721E when
building for J7200 boards.
Signed-off-by: Andrew Davis <[email protected]>
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Manorit Chawdhry <[email protected]> says:
The series adds support for J742S2 family of SoCs. Also adds J742S2 EVM
Support and re-uses most of the stuff from the superset device J784s4.
This device is a subset of J784S4 and shares the same memory map and
thus the code is being reused from J784S4 to avoid duplication.
It initially cleans up the J784s4 and AM69 files so that they can be
re-usable for j742s2 and then it introduces J742S2.
The DT for the following SoC will be coming to U-boot during 6.13 Sync
so the series is kept as RFC till then.
Here are some of the salient features of the J742S2 automotive grade
application processor:
The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.
Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch
* 2 DDR controller vs 4 DDR controller
Test logs:
https://gist.github.com/manorit2001/f7df0e8cca1e9973b4361f0559c6f53d
Link: https://lore.kernel.org/r/[email protected]
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Re-use j784s4 clocks and power domains for j742s2 family of device.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
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Christian Marangi <[email protected]> says:
This little series adds initial support for Airoha AN7581 SoC.
With the help of some backport patch, this use OF_UPSTREAM
directly.
Posting this to have the targer and the very basic driver.
Ethernet, SNAND and eMMC support is already ready downstream
and will be posted shortly after this gets approved.
Having the first driver ready permits to separately push
dedicate series for SNAND, eMMC and Ethrnet as they all depends
on basic support of clock and reset and nothing else.
Link: https://lore.kernel.org/r/[email protected]
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Add driver for controlling the reset lines of AN7581. This is a detached
version of the clock controller driver present in Linux only used to
control reset lines. Driver gets loaded with the bind of the clock
driver and doesn't require a compatible. This is needed as they share
the same registers.
Signed-off-by: Christian Marangi <[email protected]>
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Add support for Airoha AN7581 SoC clock driver. This mainly needed for
eMMC support to correctly get the current clock applied.
Based on the Linux clk-en7523.c but majorly reworked for U-Boot that
doesn't require CCF subsystem.
Major modification, support for set_rate, realtime get_rate and split
for reset part to a different driver.
Signed-off-by: Christian Marangi <[email protected]>
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The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Jernej Skrabec <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25324
- Imply the i.MX thermal driver by default on imx8, imx9, imx8m.
- Add clk_resolve_parent_clk() and fix up iMX clock drivers.
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These helpers wrongly return the updated register value. As a non-zero
value indicates failure, this causes various clock operations are
considered failed.
Correct the return value to constant zero, since these simple MMIO
operations won't fail. This fixes clock enabling failures during booting
process,
In: serial@4140000
Out: serial@4140000
Err: serial@4140000
Net: Enable clock-controller@3002000 failed
failed to enable clock 0
No ethernet found.
which leads to misoperation of various peripherals.
Fixes: 5f364e072e7 ("clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC")
Tested-by: Yuguo Pei <[email protected]>
Signed-off-by: Yao Zi <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
qcom-next-20230324:
* msm8916 gets proper sysreset and spin-table support
* The first new IPQ platform is added - the IPQ9574. The IPQ series are
used in routers. The flashing process is also documented
* mach-snapdragon gains the ability to boot with an internal FDT and
still parse memory from an externally provided one
* SC7280 gets a pinctrl driver and various clock driver improvements.
* Qualcom clock drivers will now actually return an error when
attempting
to enable a clock which isn't described.
* Qualcomm pinctrl drivers will now return an error when attempting to
configure an invalid function mux
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Pass struct udevice * into imx_clk_fixed_factor*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <[email protected]>
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Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <[email protected]>
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Use U-Boot specific struct udevice instead of Linux compatibility
struct device in clk-fixed-factor registration.
Signed-off-by: Marek Vasut <[email protected]>
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Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <[email protected]>
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Pass struct udevice * into imx_clk_divider*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <[email protected]>
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