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2023-12-14Merge tag 'xilinx-for-v2024.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2024.04-rc1 zynqmp: - Introduce Kria specific defconfig - Calculate SPI image location based on boot offset - DT updates zynqmp-clk: - Fix topsw_lsbus_clock for DP axi-enet: - Support older DT binding mailbox: - Add support for multiple mailboxes pcie-xilinx: - Covert driver to newer interface - Enable MMIO region zynq: - dfu updates - Enable capsule update for Antminer S9 - DT updates xilinx_spi: - Add new xfer callback and support runtime fifo depth discovery
2023-12-13clk: zynqmp: enable topsw_lsbus clockVenkatesh Yadav Abbarapu
Display port is using topsw_lsbus clock, it is failing while enabling the clock, so enable the topsw_lsbus clock. Signed-off-by: Sreekanth Sunnam <[email protected]> Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-12-13clk: imx8mn: add pwm clocksNicolas Heemeryck
Based on Linux kernel 6.7-rc4, add necessary clocks for the PWM controllers. Signed-off-by: Nicolas Heemeryck <[email protected]> Reviewed-by: Fabio Estevam <[email protected]>
2023-12-05clk: starfive: jh7110: Add watchdog clocksChanho Park
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-12-04Merge tag 'v2024.01-rc4' into nextTom Rini
Prepare v2024.01-rc4 # -----BEGIN PGP SIGNATURE----- # # iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmVuHrwACgkQFHw5/5Y0 # tyy3Tgv+LB/X0ZR3IHnu1mvQ7kpOFvAjjKr0BUpcEEzsrDZeJnS6sy06m+REez2E # UmuLeKFj5NUCYXNKtxn2+gVnJt8Tk6ftxhMTiZHmR4Y4NVc5aPtqYmVsv6Q29j0U # mcg7AGcZTniu9/naNM+ZcDeHzLDAB0whmE9eVfixXVgyitILoLHNdFiQ7W4oR7Kh # /mBgdMDBS3rqiRi6CuqKUnl4ADX8T3AXaSfi3hqOC5Pj+HPkZSUfyWx31mu9mN1D # wXTHASZX06Dop25fm/ZSdWk1blBw29WqRiJBdwNatvyC5pqMsotTvAfH2AcHBEYg # tpoper+WDOBAipt6b6Y1B7q4VPvJ97L9dFCAYqN0nGCe+rkdi+k+cly7M6Ye9xLt # e7rVUfnKgIMP8jkLcVBYoWkFY5FiJ82O5qjoF5N3dAuHeWacDFsB5TugDTOQvblH # LWCmcIyU1N9Ma/Ib0rTvNduvpBUYBKXYlD1+rjPZUbTUnfc79mf+ReFpcoW6Kxh+ # bkz81p8P # =ebIZ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Dec 2023 01:47:24 PM EST # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <[email protected]>" [ultimate]
2023-11-28Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini
2023-11-20Merge tag 'v2024.01-rc3' into nextTom Rini
Prepare v2024.01-rc3
2023-11-16treewide: use linux/time.h for time conversion definesIgor Prusov
Now that we have time conversion defines from in time.h there is no need for each driver to define their own version. Signed-off-by: Igor Prusov <[email protected]> Reviewed-by: Svyatoslav Ryhel <[email protected]> # tegra Reviewed-by: Eugen Hristev <[email protected]> #at91 Reviewed-by: Caleb Connolly <[email protected]> #qcom geni Reviewed-by: Stefan Bosch <[email protected]> #nanopi2 Reviewed-by: Patrice Chotard <[email protected]>
2023-11-13clk: exynos: Add header guard for clk-pll.hSam Protsenko
The clk-pll.h is going to be included in multiple files soon. Add missing header guard to prevent possible build errors in future. Signed-off-by: Sam Protsenko <[email protected]> Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc") Reviewed-by: Sean Anderson <[email protected]> Signed-off-by: Minkyu Kang <[email protected]>
2023-11-12clk: sunxi: Use the right symbol in the MakefileSamuel Holland
CONFIG_ARCH_SUNXI will not be enabled for RISC-V SoCs using this driver. Use the symbol for the driver itself instead. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]>
2023-11-10tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <[email protected]>
2023-11-07clk_k210.c: Clean up how we handle nopTom Rini
Now that sandbox has <asm/barrier.h> and defines nop() there we should include that in our driver for clarity and then remove our local nop() from <k210/pll.h>. Reviewed-by: Sean Anderson <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2023-11-06clk: a1: add new clocks for USB stackAlexey Romanov
Since we sync device tree with Linux, we have to add this clock definition for USB stack. Signed-off-by: Alexey Romanov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
2023-11-02Merge branch 'master_common_h_cleanup' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-sh - Remove common.h usage
2023-11-02Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
+ CI: Use OpenSBI 1.3.1 release for testing + riscv: Support resume after exception + rng: Support RNG provided by RISC-V Zkr ISA extension + board: starfive VF2: Support jtag + board: starfive VF2: Support TRNG driver + board: sifive unmatched: Move kernel load address
2023-11-02clk: rzg2l: Drop <common.h>Paul Barker
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker <[email protected]>
2023-11-02clk: starfive: jh7110: Add security clocksChanho Park
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-11-01Merge tag 'clk-2024.01-rc2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-clk Clock changes for 2024.01-rc2 This contains several fixes for the clock core.
2023-11-01clk: use private clk struct in CLK_CCF's enable/disable functionsMaksim Kiselev
In clk_enable()/clk_disable() functions, when CCF is activated, we must pass a private clk struct to enable()/disable() ops functions. Otherwise, the use of a container_of() construction within these ops should be banned. Because passing a non-private clk struct to container_of() results in an out of range error. At the moment, clk-mux, clk-fixed-factor, clk-gate and possibly other clocks use container_of() in their enable()/disable() functions. Therefore, for these functions to work correclty, private clk struct must be passed. Signed-off-by: Maksim Kiselev <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-11-01clk: fix count parameter type for clk_release_allEugen Hristev
The second parameter for clk_release_all is used as an unsigned (which makes sense) but the function prototype declares it as an int. This causes warnings/error like such below: include/clk.h:422:48: error: conversion to ‘int’ from ‘unsigned int’ may change the sign of the result [-Werror=sign-conversion] 422 | return clk_release_all(bulk->clks, bulk->count); To fix this, changed the type of the count to `unsigned int` Fixes: 82a8a669b4f7 ("clk: add clk_release_all()") Signed-off-by: Eugen Hristev <[email protected]> Reviewed-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-11-01drivers: clk: Adjust temp var data type to properly match that of struct clk_opsNathan Barrett-Morrison
In commit 5c5992cb90cf ("clk: Add debugging for return values"), a temporary storage variable was added around the ops->get_rate() call inside clk_get_rate(), so that the result could be passed through log_ret. This temporary variable was declared as an int, yet when we look in struct clk_ops, we can see this needs to be a ulong: ulong (*get_rate)(struct clk *clk); This was resulting in a signed to unsigned casting error on our builds, where a clock value of 0xABCDABCD was being incorrectly cast to 0xFFFFFFFFABCDABCD. Signed-off-by: Nathan Barrett-Morrison <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-10-31clk: ti: k3-pll: Add calibration support for non fractional modeVishal Mahaveer
PLL calibration needs to be enabled when operating in non fractional mode. Add the sequence to do a fast calibration when using PLL in this mode. Signed-off-by: Vishal Mahaveer <[email protected]>
2023-10-24Merge tag 'u-boot-rockchip-20231024' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus; - clk driver fix for rk3568 and rk3588; - rkmtd cmd support for rockchip nand device; - dts update and sync from linux;
2023-10-23clk: rockchip: rk3588: fix up the frac pll calculationElaine Zhang
rk3588 frac pll: FFVCO = ((m + k / 65536) * FFIN) / p FFOUT = ((m + k / 65536) * FFIN) / (p * 2s) k is the original code, but the K[15:0] is complement code (6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111), need to be converted. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-10-23clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parentElaine Zhang
Optimize setting process. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-10-23clk: rockchip: rk3588: support aclk_top_root set 750MElaine Zhang
aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-10-23clk: rk3588: Add 742.5M parameter for PLLGuochun Huang
For a specific frequency. Signed-off-by: Guochun Huang <[email protected]> Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-10-23clk: rockchip: rk3568: support dclk_vop select more parent clksElaine Zhang
For dclk_vop to support more frequencies. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-10-22sunxi: add Allwinner R528/T113 SoC supportAndre Przywara
This adds the remaining code bits to teach U-Boot about Allwinner's newest SoC generation. This was introduced with the RISC-V based Allwinner D1 SoC, which actually shares a die with the ARM cores versions called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM). This adds the new Kconfig stanza, using the two newly introduced symbols for the new SoC generation and pincontroller. It also adds the new symbols to the relavent code places, to set all the hardcoded bits directly. We need one DT override: The ARM core version of the DT specifies the CPUX watchdog as "reserved", which means it won't be recognised by U-Boot. Override this in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog, so that the generic reset driver will work. Signed-off-by: Andre Przywara <[email protected]>
2023-10-22clk: sunxi: Add support for the D1 CCUSamuel Holland
Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Acked-by: Sean Anderson <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-10-17Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
- RZ/G2L part 1, except for two serial port patches which I had to drop as they broke R2Dplus, they will come later via subsequent PR.
2023-10-16Merge tag 'u-boot-imx-20231016' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20231016 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18168 - Imrovement MX93 - Toradex: fixes - Convert to DM (serial, watchdog) for some boards - HAB improvements for Secure Boot - DTO overlay for DHCOM - USB fixes, Mass storage for MX28 - Cleanup some code - Phytec MX8M : EEProm detection, fixes - Gateworks Boards improvements
2023-10-16clk: renesas: Add RZ/G2L & RZ/G2LC CPG driverPaul Barker
This driver provides clock and reset control for the Renesas R9A07G044L (RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts: * driver code which is applicable to all SoCs in the RZ/G2L family. * static data describing the clocks and resets which are specific to the R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter) is used to indicate that both SoCs are supported. clk_set_rate() and clk_get_rate() are implemented only for the clocks that are actually used in u-boot. The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind function is called before the SCIF (serial port) driver is probed. This is required so that we can de-assert the relevant reset signal during the serial driver probe function. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Lad Prabhakar <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-10-16Merge tag 'u-boot-amlogic-20231015' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - add Amlogic A1 clock driver - add Amlogic A1 reset support - add USB Device support for Amlogic A1 - enable RNG on Amlogic A1 & Amlogic S4 - move Amlogic Secure Monitor to standalone driver
2023-10-16clk: imx: add i.MX93 CCF driverSébastien Szymanski
Add i.MX93 CCF driver support. Modifed from Linux Kernel v6.5-rc2 and adapted for U-Boot. Signed-off-by: Sébastien Szymanski <[email protected]>
2023-10-13scmi: refactor the code to hide a channel from devicesAKASHI Takahiro
The commit 85dc58289238 ("firmware: scmi: prepare uclass to pass channel reference") added an explicit parameter, channel, but it seems to make the code complex. Hiding this parameter will allow for adding a generic (protocol-agnostic) helper function, i.e. for PROTOCOL_VERSION, in a later patch. Signed-off-by: AKASHI Takahiro <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Etienne Carriere <[email protected]>
2023-10-13Merge tag 'xilinx-for-v2024.01-rc1-v3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2024.01-rc1 v3 clk: - remove additional compatible strings for Versal NET net: - zynq_gem: Fix clock calculation for MDC for higher frequencies pinctrl: - core: Extend pinmux status buffere size - zynqmp driver: Show also tristate configuration test: - add test case for pxe get Xilinx: - describe SelectMAP boot mode Zynq: - Fix nand description in DT ZynqMP: - DTS sync patches with kernel and also W=1 related fixes - Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c description for other SC based boards - k24 psu_init cleanup
2023-10-12clk: ti: clk-sci: Notify AVS driver based upon clock rateUdit Kumar
AVS driver needs to be notified before or after clock change, depending upon new rate is greater or less than current clock rate. Fixes: 1e0aa873bc7cd ("clk: clk-ti-sci: Notify AVS driver upon setting clock rate") Cc: Keerthy <[email protected]> Signed-off-by: Udit Kumar <[email protected]>
2023-10-12clk: ti: clk-k3: Notify AVS driver upon setting clock rateUdit Kumar
AVS is enabled at R5 SPL stage, on few platforms like J721E and J7200 clk-k3 is used instead if clk-sci driver. Add support in clk-k3 driver as well to notify AVS driver on setting clock rate so that voltage is changed accordingly. Cc: Keerthy <[email protected]> Signed-off-by: Udit Kumar <[email protected]>
2023-10-12a1: clk: Add missing USB_PHY_IN and USB_PHY gatesIgor Prusov
We use this clocks in dwc3 driver. Signed-off-by: Igor Prusov <[email protected]> Signed-off-by: Alexey Romanov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
2023-10-12clk: Add clock driver for Amlogic A1Igor Prusov
This patch adds basic clock driver for Amlogic A1 Family which supports enabling/disabling some gates, getting frequencies and setting rate with limited reparenting. Signed-off-by: Igor Prusov <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
2023-10-09Revert "clk: versal: Enable clock driver for Versal NET"Michal Simek
This partially reverts commit ff33227819f579ffb963e0dac6bc6a6566b89563. Versal NET clock node should use "xlnx,versal-net-clk", "xlnx,versal-clk" compatible string that's why it is not necessary to define Versal NET specific compatible string if there is no any other change needed. It can be get back if there is a need to differentiate clock support between Versal and Versal NET. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c09276022db5f1b150679cc7a9f9583363ace2fb.1695808971.git.michal.simek@amd.com
2023-10-04Merge tag 'u-boot-stm32-20231004' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm STM32 MCU: _ alignment with kernel DT v6.5 for stm32f429 and stm32f746 _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco STM32 MPU: _ alignment with kernel DT v6.6-rc1 _ add RNG support for stm32mp13 _ add USB, USB boot and stm32prog command support for stm32mp13 _ add support of USART1 clock for stm32mp1 _ only print RAM and board code with SPL_DISPLAY_PRINT flag for stm32mp1 _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc for stm32mp15xx DHCOR [ Fix merge conflict at board/st/common/stm32mp_dfu.c ] Signed-off-by: Tom Rini <[email protected]>
2023-10-04clk: stm32mp1: Add support for USART1 clockAnatolij Gustschin
Add USART1 clock parents and mux configuration. This allows support for configuring the USART1 as the serial console in SPL and U-Boot via device tree. Without this patch the SPL with usart1 serial console enabled crashes because it can not find the clock specified in the device tree for usart1. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2023-10-02Merge branch 'next_pinctrl_sync' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-sh - pinctrl re-sync for Renesas chips
2023-10-02Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2023-10-01clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
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